[platform/devel-riscv-v2 PATCHv5 08/18] U5SeriesPkg/RiscVPlatformTimerLib: Platform Timer library

["Abner Chang" <abner.chang@hpe.com>]

Timer library used to access to machine mode timer Control Status Registers
for U5 series platforms.

Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
 .../RiscVPlatformTimerLib.inf                      | 36 ++++++++++++++++
 Platform/SiFive/U5SeriesPkg/Include/U5Clint.h      | 20 +++++++++
 .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.S  | 48 ++++++++++++++++++++++
 3 files changed, 104 insertions(+)
 create mode 100644 Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
 create mode 100644 Platform/SiFive/U5SeriesPkg/Include/U5Clint.h
 create mode 100644 Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S

diff --git a/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
new file mode 100644
index 0000000..777ec98
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
@@ -0,0 +1,36 @@
+## @file
+# RISC-V CPU lib to override timer mechanism for U5 series platform.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001b
+  BASE_NAME                      = RiscVPlatformTimerLib
+  FILE_GUID                      = AFA75BBD-DE9D-4E77-BD88-1EA401BE931D
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RiscVPlatformTimerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+  RiscVPlatformTimerLib.S
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+  RiscVPkg/RiscVPkg.dec
+
+
+
diff --git a/Platform/SiFive/U5SeriesPkg/Include/U5Clint.h b/Platform/SiFive/U5SeriesPkg/Include/U5Clint.h
new file mode 100644
index 0000000..26260dc
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Include/U5Clint.h
@@ -0,0 +1,20 @@
+/** @file
+  RISC-V Timer Architectural definition for U500 platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef U5_CLINT_H_
+#define U5_CLINT_H_
+
+#define CLINT_REG_BASE_ADDR 0x02000000
+    #define CLINT_REG_MTIME     0x0200BFF8
+    #define CLINT_REG_MTIMECMP0 0x02004000
+    #define CLINT_REG_MTIMECMP1 0x02004008
+    #define CLINT_REG_MTIMECMP2 0x02004010
+    #define CLINT_REG_MTIMECMP3 0x02004018
+    #define CLINT_REG_MTIMECMP4 0x02004020
+
+#endif
diff --git a/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S
new file mode 100644
index 0000000..a49149e
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+//
+// SiFive U5 Series Timer CSR functions.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+#include <RiscVImpl.h>
+#include <U5Clint.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVReadMachineTimer)
+.global ASM_PFX(RiscVSetMachineTimerCmp)
+.global ASM_PFX(RiscVReadMachineTimerCmp)
+
+//
+// Read machine timer CSR.
+// @retval a0 : 64-bit machine timer.
+//
+ASM_PFX (RiscVReadMachineTimer):
+    li t1, CLINT_REG_MTIME
+    ld a0, (t1)
+    ret
+
+//
+// Set machine timer compare CSR.
+// @param a0 : UINT64
+//
+ASM_PFX (RiscVSetMachineTimerCmp):
+    li t1, CLINT_REG_MTIMECMP0
+    sd a0, (t1)
+    ret
+
+//
+// Read machine timer compare CSR.
+// @param a0 : UINT64
+//
+ASM_PFX (RiscVReadMachineTimerCmp):
+    li t1, CLINT_REG_MTIMECMP0
+    ld a0, (t1)
+    ret
-- 
2.7.4