From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web11.2343.1572238367898248469 for ; Sun, 27 Oct 2019 21:52:48 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=02044412f4=abner.chang@hpe.com) Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S4psIV013292; Mon, 28 Oct 2019 04:52:47 GMT Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2vvbnuj0v5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 04:52:47 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 7FE6D54; Mon, 28 Oct 2019 04:52:46 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 759614A; Mon, 28 Oct 2019 04:52:44 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Michael D Kinney , Ard Biesheuvel , Leif Lindholm , Gilbert Chen , Palmer Dabbelt Subject: [platform/devel-riscv-v2 PATCHv5 08/18] U5SeriesPkg/RiscVPlatformTimerLib: Platform Timer library Date: Mon, 28 Oct 2019 12:20:23 +0800 Message-Id: <1572236433-15404-9-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572236433-15404-1-git-send-email-abner.chang@hpe.com> References: <1572236433-15404-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-28_01:2019-10-25,2019-10-28 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 mlxscore=0 phishscore=0 bulkscore=0 impostorscore=0 malwarescore=0 mlxlogscore=719 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=13 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1910280047 Timer library used to access to machine mode timer Control Status Registers for U5 series platforms. Signed-off-by: Abner Chang Cc: Michael D Kinney Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Gilbert Chen Cc: Palmer Dabbelt Signed-off-by: Abner Chang --- .../RiscVPlatformTimerLib.inf | 36 ++++++++++++++++ Platform/SiFive/U5SeriesPkg/Include/U5Clint.h | 20 +++++++++ .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.S | 48 ++++++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf create mode 100644 Platform/SiFive/U5SeriesPkg/Include/U5Clint.h create mode 100644 Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S diff --git a/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf new file mode 100644 index 0000000..777ec98 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf @@ -0,0 +1,36 @@ +## @file +# RISC-V CPU lib to override timer mechanism for U5 series platform. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = RiscVPlatformTimerLib + FILE_GUID = AFA75BBD-DE9D-4E77-BD88-1EA401BE931D + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RiscVPlatformTimerLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + +[Sources.RISCV64] + RiscVPlatformTimerLib.S + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec + RiscVPkg/RiscVPkg.dec + + + diff --git a/Platform/SiFive/U5SeriesPkg/Include/U5Clint.h b/Platform/SiFive/U5SeriesPkg/Include/U5Clint.h new file mode 100644 index 0000000..26260dc --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/Include/U5Clint.h @@ -0,0 +1,20 @@ +/** @file + RISC-V Timer Architectural definition for U500 platform. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef U5_CLINT_H_ +#define U5_CLINT_H_ + +#define CLINT_REG_BASE_ADDR 0x02000000 + #define CLINT_REG_MTIME 0x0200BFF8 + #define CLINT_REG_MTIMECMP0 0x02004000 + #define CLINT_REG_MTIMECMP1 0x02004008 + #define CLINT_REG_MTIMECMP2 0x02004010 + #define CLINT_REG_MTIMECMP3 0x02004018 + #define CLINT_REG_MTIMECMP4 0x02004020 + +#endif diff --git a/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S new file mode 100644 index 0000000..a49149e --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S @@ -0,0 +1,48 @@ +//------------------------------------------------------------------------------ +// +// SiFive U5 Series Timer CSR functions. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------------ +#include +#include +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVReadMachineTimer) +.global ASM_PFX(RiscVSetMachineTimerCmp) +.global ASM_PFX(RiscVReadMachineTimerCmp) + +// +// Read machine timer CSR. +// @retval a0 : 64-bit machine timer. +// +ASM_PFX (RiscVReadMachineTimer): + li t1, CLINT_REG_MTIME + ld a0, (t1) + ret + +// +// Set machine timer compare CSR. +// @param a0 : UINT64 +// +ASM_PFX (RiscVSetMachineTimerCmp): + li t1, CLINT_REG_MTIMECMP0 + sd a0, (t1) + ret + +// +// Read machine timer compare CSR. +// @param a0 : UINT64 +// +ASM_PFX (RiscVReadMachineTimerCmp): + li t1, CLINT_REG_MTIMECMP0 + ld a0, (t1) + ret -- 2.7.4