[edk2-platforms] [PATCH v2 03/11] SocLib : Add support for initialization of peripherals

["Meenakshi Aggarwal" <meenakshi.aggarwal@nxp.com>]

Add SocInit function that initializes peripherals
and print board and soc information.

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf |  45 ++
 Silicon/NXP/Include/Chassis2/LsSerDes.h      |  62 +++
 Silicon/NXP/Include/Chassis2/NxpSoc.h        | 361 ++++++++++++++
 Silicon/NXP/Include/DramInfo.h               |  38 ++
 Silicon/NXP/LS1043A/Include/SocSerDes.h      |  51 ++
 Silicon/NXP/Library/SocLib/NxpChassis.h      | 136 ++++++
 Silicon/NXP/Library/SocLib/Chassis.c         | 498 ++++++++++++++++++++
 Silicon/NXP/Library/SocLib/Chassis2/Soc.c    | 162 +++++++
 Silicon/NXP/Library/SocLib/SerDes.c          | 268 +++++++++++
 9 files changed, 1621 insertions(+)

diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
new file mode 100644
index 000000000000..cb670a12797e
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -0,0 +1,45 @@
+#  @file
+#
+#  Copyright 2017-2019 NXP
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = SocLib
+  FILE_GUID                      = e868c5ca-9729-43ae-bff4-438c67de8c68
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SocLib
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/NXP/NxpQoriqLs.dec
+  Silicon/NXP/LS1043A/LS1043A.dec
+
+[LibraryClasses]
+  ArmSmcLib
+  BaseLib
+  DebugLib
+  IoAccessLib
+  SerialPortLib
+
+[Sources.common]
+  Chassis.c
+  Chassis2/Soc.c
+  SerDes.c
+
+[BuildOptions]
+  GCC:*_*_*_CC_FLAGS = -DCHASSIS2
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+  gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+  gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+  gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
+  gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h
new file mode 100644
index 000000000000..9afbc522398a
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis2/LsSerDes.h
@@ -0,0 +1,62 @@
+/** LsSerDes.h
+ The Header file of SerDes Module for Chassis 2
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef LS_SERDES_H_
+#define LS_SERDES_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#define SRDS_MAX_LANES     4
+
+typedef enum {
+  None = 0,
+  Pcie1,
+  Pcie2,
+  Pcie3,
+  Sata,
+  SgmiiFm1Dtsec1,
+  SgmiiFm1Dtsec2,
+  SgmiiFm1Dtsec5,
+  SgmiiFm1Dtsec6,
+  SgmiiFm1Dtsec9,
+  SgmiiFm1Dtsec10,
+  QsgmiiFm1A,
+  XfiFm1Mac9,
+  XfiFm1Mac10,
+  Sgmii2500Fm1Dtsec2,
+  Sgmii2500Fm1Dtsec5,
+  Sgmii2500Fm1Dtsec9,
+  Sgmii2500Fm1Dtsec10,
+  SerdesPrtclCount
+} SERDES_PROTOCOL;
+
+typedef enum {
+  Srds1  = 0,
+  Srds2,
+  SrdsMaxNum
+} SERDES_NUMBER;
+
+typedef struct {
+  UINT16 Protocol;
+  UINT8  SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef VOID
+(*SERDES_PROBE_LANES_CALLBACK) (
+  IN SERDES_PROTOCOL LaneProtocol,
+  IN VOID *Arg
+  );
+
+VOID
+SerDesProbeLanes(
+  IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+  IN VOID *Arg
+  );
+
+#endif /* LS_SERDES_H_ */
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
new file mode 100644
index 000000000000..f05a813750e8
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -0,0 +1,361 @@
+/** Soc.h
+*  Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+*  Copyright 2017-2019 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef NXP_SOC_H_
+#define NXP_SOC_H_
+
+#define HWA_CGA_M1_CLK_SEL         0xe0000000
+#define HWA_CGA_M1_CLK_SHIFT       29
+
+#define TP_CLUSTER_EOC_MASK        0xc0000000  /* end of clusters mask */
+#define NUM_CC_PLLS                2
+#define CLK_FREQ                   100000000
+#define MAX_CPUS                   4
+#define NUM_FMAN                   1
+#define CHECK_CLUSTER(Cluster)    ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
+
+/* RCW SERDES MACRO */
+#define RCWSR_INDEX                4
+#define RCWSR_SRDS1_PRTCL_MASK     0xffff0000
+#define RCWSR_SRDS1_PRTCL_SHIFT    16
+#define RCWSR_SRDS2_PRTCL_MASK     0x0000ffff
+#define RCWSR_SRDS2_PRTCL_SHIFT    0
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR             0x09000000
+#define SMMU_REG_SCR0              (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR              (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1              (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0             (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR             (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK           0x00000400
+#define SCR0_CLIENTPD_MASK         0x00000001
+#define SACR_PAGESIZE_MASK         0x00010000
+#define IDR1_PAGESIZE_MASK         0x80000000
+
+typedef struct {
+  UINTN FreqProcessor[MAX_CPUS];
+  UINTN FreqSystemBus;
+  UINTN FreqDdrBus;
+  UINTN FreqLocalBus;
+  UINTN FreqSdhc;
+  UINTN FreqFman[NUM_FMAN];
+  UINTN FreqQman;
+} SYS_INFO;
+
+/* Device Configuration and Pin Control */
+typedef struct {
+  UINT32   PorSr1;         /* POR status 1 */
+#define CHASSIS2_CCSR_PORSR1_RCW_MASK  0xFF800000
+  UINT32   PorSr2;         /* POR status 2 */
+  UINT8    Res008[0x20-0x8];
+  UINT32   GppOrCr1;       /* General-purpose POR configuration */
+  UINT32   GppOrCr2;
+  UINT32   DcfgFuseSr;    /* Fuse status register */
+  UINT8    Res02c[0x70-0x2c];
+  UINT32   DevDisr;        /* Device disable control */
+  UINT32   DevDisr2;       /* Device disable control 2 */
+  UINT32   DevDisr3;       /* Device disable control 3 */
+  UINT32   DevDisr4;       /* Device disable control 4 */
+  UINT32   DevDisr5;       /* Device disable control 5 */
+  UINT32   DevDisr6;       /* Device disable control 6 */
+  UINT32   DevDisr7;       /* Device disable control 7 */
+  UINT8    Res08c[0x94-0x8c];
+  UINT32   CoreDisrU;      /* uppper portion for support of 64 cores */
+  UINT32   CoreDisrL;      /* lower portion for support of 64 cores */
+  UINT8    Res09c[0xa0-0x9c];
+  UINT32   Pvr;            /* Processor version */
+  UINT32   Svr;            /* System version */
+  UINT32   Mvr;            /* Manufacturing version */
+  UINT8    Res0ac[0xb0-0xac];
+  UINT32   RstCr;          /* Reset control */
+  UINT32   RstRqPblSr;     /* Reset request preboot loader status */
+  UINT8    Res0b8[0xc0-0xb8];
+  UINT32   RstRqMr1;       /* Reset request mask */
+  UINT8    Res0c4[0xc8-0xc4];
+  UINT32   RstRqSr1;       /* Reset request status */
+  UINT8    Res0cc[0xd4-0xcc];
+  UINT32   RstRqWdTmrL;     /* Reset request WDT mask */
+  UINT8    Res0d8[0xdc-0xd8];
+  UINT32   RstRqWdtSrL;     /* Reset request WDT status */
+  UINT8    Res0e0[0xe4-0xe0];
+  UINT32   BrrL;            /* Boot release */
+  UINT8    Res0e8[0x100-0xe8];
+  UINT32   RcwSr[16];      /* Reset control word status */
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT  25
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK  0x1f
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT  16
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK  0x3f
+  UINT8    Res140[0x200-0x140];
+  UINT32   ScratchRw[4];   /* Scratch Read/Write */
+  UINT8    Res210[0x300-0x210];
+  UINT32   ScratcHw1R[4];  /* Scratch Read (Write once) */
+  UINT8    Res310[0x400-0x310];
+  UINT32   CrstSr[12];
+  UINT8    Res430[0x500-0x430];
+  /* PCI Express n Logical I/O Device Number register */
+  UINT32   DcfgCcsrPex1LiodNr;
+  UINT32   DcfgCcsrPex2LiodNr;
+  UINT32   DcfgCcsrPex3LiodNr;
+  UINT32   DcfgCcsrPex4LiodNr;
+  /* RIO n Logical I/O Device Number register */
+  UINT32   DcfgCcsrRio1LiodNr;
+  UINT32   DcfgCcsrRio2LiodNr;
+  UINT32   DcfgCcsrRio3LiodNr;
+  UINT32   DcfgCcsrRio4LiodNr;
+  /* USB Logical I/O Device Number register */
+  UINT32   DcfgCcsrUsb1LiodNr;
+  UINT32   DcfgCcsrUsb2LiodNr;
+  UINT32   DcfgCcsrUsb3LiodNr;
+  UINT32   DcfgCcsrUsb4LiodNr;
+  /* SD/MMC Logical I/O Device Number register */
+  UINT32   DcfgCcsrSdMmc1LiodNr;
+  UINT32   DcfgCcsrSdMmc2LiodNr;
+  UINT32   DcfgCcsrSdMmc3LiodNr;
+  UINT32   DcfgCcsrSdMmc4LiodNr;
+  /* RIO Message Unit Logical I/O Device Number register */
+  UINT32   DcfgCcsrRiomaintLiodNr;
+  UINT8    Res544[0x550-0x544];
+  UINT32   SataLiodNr[4];
+  UINT8    Res560[0x570-0x560];
+  UINT32   DcfgCcsrMisc1LiodNr;
+  UINT32   DcfgCcsrMisc2LiodNr;
+  UINT32   DcfgCcsrMisc3LiodNr;
+  UINT32   DcfgCcsrMisc4LiodNr;
+  UINT32   DcfgCcsrDma1LiodNr;
+  UINT32   DcfgCcsrDma2LiodNr;
+  UINT32   DcfgCcsrDma3LiodNr;
+  UINT32   DcfgCcsrDma4LiodNr;
+  UINT32   DcfgCcsrSpare1LiodNr;
+  UINT32   DcfgCcsrSpare2LiodNr;
+  UINT32   DcfgCcsrSpare3LiodNr;
+  UINT32   DcfgCcsrSpare4LiodNr;
+  UINT8    Res5a0[0x600-0x5a0];
+  UINT32   DcfgCcsrPblSr;
+  UINT32   PamuBypENr;
+  UINT32   DmaCr1;
+  UINT8    Res60c[0x610-0x60c];
+  UINT32   DcfgCcsrGenSr1;
+  UINT32   DcfgCcsrGenSr2;
+  UINT32   DcfgCcsrGenSr3;
+  UINT32   DcfgCcsrGenSr4;
+  UINT32   DcfgCcsrGenCr1;
+  UINT32   DcfgCcsrGenCr2;
+  UINT32   DcfgCcsrGenCr3;
+  UINT32   DcfgCcsrGenCr4;
+  UINT32   DcfgCcsrGenCr5;
+  UINT32   DcfgCcsrGenCr6;
+  UINT32   DcfgCcsrGenCr7;
+  UINT8    Res63c[0x658-0x63c];
+  UINT32   DcfgCcsrcGenSr1;
+  UINT32   DcfgCcsrcGenSr0;
+  UINT8    Res660[0x678-0x660];
+  UINT32   DcfgCcsrcGenCr1;
+  UINT32   DcfgCcsrcGenCr0;
+  UINT8    Res680[0x700-0x680];
+  UINT32   DcfgCcsrSrIoPstecr;
+  UINT32   DcfgCcsrDcsrCr;
+  UINT8    Res708[0x740-0x708]; /* add more registers when needed */
+  UINT32   TpItyp[64];          /* Topology Initiator Type Register */
+  struct {
+    UINT32 Upper;
+    UINT32 Lower;
+  } TpCluster[16];
+  UINT8    Res8c0[0xa00-0x8c0]; /* add more registers when needed */
+  UINT32   DcfgCcsrQmBmWarmRst;
+  UINT8    Resa04[0xa20-0xa04]; /* add more registers when needed */
+  UINT32   DcfgCcsrReserved0;
+  UINT32   DcfgCcsrReserved1;
+} CCSR_GUR;
+
+/* Supplemental Configuration Unit */
+typedef struct {
+  UINT8  Res000[0x070-0x000];
+  UINT32 Usb1Prm1Cr;
+  UINT32 Usb1Prm2Cr;
+  UINT32 Usb1Prm3Cr;
+  UINT32 Usb2Prm1Cr;
+  UINT32 Usb2Prm2Cr;
+  UINT32 Usb2Prm3Cr;
+  UINT32 Usb3Prm1Cr;
+  UINT32 Usb3Prm2Cr;
+  UINT32 Usb3Prm3Cr;
+  UINT8  Res094[0x100-0x094];
+  UINT32 Usb2Icid;
+  UINT32 Usb3Icid;
+  UINT8  Res108[0x114-0x108];
+  UINT32 DmaIcid;
+  UINT32 SataIcid;
+  UINT32 Usb1Icid;
+  UINT32 QeIcid;
+  UINT32 SdhcIcid;
+  UINT32 EdmaIcid;
+  UINT32 EtrIcid;
+  UINT32 Core0SftRst;
+  UINT32 Core1SftRst;
+  UINT32 Core2SftRst;
+  UINT32 Core3SftRst;
+  UINT8  Res140[0x158-0x140];
+  UINT32 AltCBar;
+  UINT32 QspiCfg;
+  UINT8  Res160[0x180-0x160];
+  UINT32 DmaMcr;
+  UINT8  Res184[0x188-0x184];
+  UINT32 GicAlign;
+  UINT32 DebugIcid;
+  UINT8  Res190[0x1a4-0x190];
+  UINT32 SnpCnfGcr;
+#define CCSR_SCFG_SNPCNFGCR_SECRDSNP         BIT31
+#define CCSR_SCFG_SNPCNFGCR_SECWRSNP         BIT30
+#define CCSR_SCFG_SNPCNFGCR_SATARDSNP        BIT23
+#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP        BIT22
+#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP        BIT21
+#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP        BIT20
+#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP        BIT15
+#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP        BIT16
+#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP        BIT13
+#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP        BIT14
+  UINT8  Res1a8[0x1ac-0x1a8];
+  UINT32 IntpCr;
+  UINT8  Res1b0[0x204-0x1b0];
+  UINT32 CoreSrEnCr;
+  UINT8  Res208[0x220-0x208];
+  UINT32 RvBar00;
+  UINT32 RvBar01;
+  UINT32 RvBar10;
+  UINT32 RvBar11;
+  UINT32 RvBar20;
+  UINT32 RvBar21;
+  UINT32 RvBar30;
+  UINT32 RvBar31;
+  UINT32 LpmCsr;
+  UINT8  Res244[0x400-0x244];
+  UINT32 QspIdQScr;
+  UINT32 EcgTxcMcr;
+  UINT32 SdhcIoVSelCr;
+  UINT32 RcwPMuxCr0;
+  /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+  *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+  *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
+  Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
+#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB      0x3333
+  /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+  *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+  *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
+  Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
+#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB  0x3300
+  UINT32 UsbDrvVBusSelCr;
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1      0x00000000
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2      0x00000001
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3      0x00000003
+  UINT32 UsbPwrFaultSelCr;
+#define CCSR_SCFG_USBPWRFAULT_INACTIVE       0x00000000
+#define CCSR_SCFG_USBPWRFAULT_SHARED         0x00000001
+#define CCSR_SCFG_USBPWRFAULT_DEDICATED      0x00000002
+#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT     4
+#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT     2
+#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT     0
+  UINT32 UsbRefclkSelcr1;
+  UINT32 UsbRefclkSelcr2;
+  UINT32 UsbRefclkSelcr3;
+  UINT8  Res424[0x600-0x424];
+  UINT32 ScratchRw[4];
+  UINT8  Res610[0x680-0x610];
+  UINT32 CoreBCr;
+  UINT8  Res684[0x1000-0x684];
+  UINT32 Pex1MsiIr;
+  UINT32 Pex1MsiR;
+  UINT8  Res1008[0x2000-0x1008];
+  UINT32 Pex2;
+  UINT32 Pex2MsiR;
+  UINT8  Res2008[0x3000-0x2008];
+  UINT32 Pex3MsiIr;
+  UINT32 Pex3MsiR;
+} CCSR_SCFG;
+
+#define USB_TXVREFTUNE        0x9
+#define USB_SQRXTUNE          0xFC7FFFFF
+#define USB_PCSTXSWINGFULL    0x47
+#define USB_PHY_RX_EQ_VAL_1   0x0000
+#define USB_PHY_RX_EQ_VAL_2   0x8000
+#define USB_PHY_RX_EQ_VAL_3   0x8003
+#define USB_PHY_RX_EQ_VAL_4   0x800b
+
+/*USB_PHY_SS memory map*/
+typedef struct {
+  UINT16 IpIdcodeLo;
+  UINT16 SupIdcodeHi;
+  UINT8  Res4[0x0006-0x0004];
+  UINT16 RtuneDebug;
+  UINT16 RtuneStat;
+  UINT16 SupSsPhase;
+  UINT16 SsFreq;
+  UINT8  ResE[0x0020-0x000e];
+  UINT16 Ateovrd;
+  UINT16 MpllOvrdInLo;
+  UINT8  Res24[0x0026-0x0024];
+  UINT16 SscOvrdIn;
+  UINT8  Res28[0x002A-0x0028];
+  UINT16 LevelOvrdIn;
+  UINT8  Res2C[0x0044-0x002C];
+  UINT16 ScopeCount;
+  UINT8  Res46[0x0060-0x0046];
+  UINT16 MpllLoopCtl;
+  UINT8  Res62[0x006C-0x0062];
+  UINT16 SscClkCntrl;
+  UINT8  Res6E[0x2002-0x006E];
+  UINT16 Lane0TxOvrdInHi;
+  UINT16 Lane0TxOvrdDrvLo;
+  UINT8  Res2006[0x200C-0x2006];
+  UINT16 Lane0RxOvrdInHi;
+  UINT8  Res200E[0x2022-0x200E];
+  UINT16 Lane0TxCmWaitTimeOvrd;
+  UINT8  Res2024[0x202A-0x2024];
+  UINT16 Lane0TxLbertCtl;
+  UINT16 Lane0RxLbertCtl;
+  UINT16 Lane0RxLbertErr;
+  UINT8  Res2030[0x205A-0x2030];
+  UINT16 Lane0TxAltBlock;
+} CCSR_USB_PHY;
+
+/* Clocking */
+typedef struct {
+  struct {
+    UINT32 ClkCnCSr;    /* core cluster n clock control status */
+    UINT8  Res004[0x0c];
+    UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
+    UINT8 Res014[0x0c];
+  } ClkcSr[4];
+  UINT8  Res040[0x780]; /* 0x100 */
+  struct {
+    UINT32 PllCnGSr;
+    UINT8  Res804[0x1c];
+  } PllCgSr[NUM_CC_PLLS];
+  UINT8  Res840[0x1c0];
+  UINT32 ClkPCSr;  /* 0xa00 Platform clock domain control/status */
+  UINT8  Resa04[0x1fc];
+  UINT32 PllPGSr;  /* 0xc00 Platform PLL General Status */
+  UINT8  Resc04[0x1c];
+  UINT32 PllDGSr;  /* 0xc20 DDR PLL General Status */
+  UINT8  Resc24[0x3dc];
+} CCSR_CLOCK;
+
+VOID
+GetSysInfo (
+  OUT SYS_INFO *
+  );
+
+UINT32
+EFIAPI
+GurRead (
+  IN  UINTN     Address
+  );
+
+#endif /* NXP_SOC_H_ */
diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
new file mode 100644
index 000000000000..a934aaeff1f5
--- /dev/null
+++ b/Silicon/NXP/Include/DramInfo.h
@@ -0,0 +1,38 @@
+/** @file
+*  Header defining the structure for Dram Information
+*
+*  Copyright 2019 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef DRAM_INFO_H_
+#define DRAM_INFO_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#define SMC_DRAM_BANK_INFO          (0xC200FF12)
+
+typedef struct {
+  UINTN            BaseAddress;
+  UINTN            Size;
+} DRAM_REGION_INFO;
+
+typedef struct {
+  UINT32            NumOfDrams;
+  UINT32            Reserved;
+  DRAM_REGION_INFO  DramRegion[3];
+} DRAM_INFO;
+
+EFI_STATUS
+GetDramBankInfo (
+  IN OUT DRAM_INFO *DramInfo
+  );
+
+VOID
+UpdateDpaaDram (
+  IN OUT DRAM_INFO *DramInfo
+  );
+
+#endif /* DRAM_INFO_H_ */
diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
new file mode 100644
index 000000000000..2d1c6f10f932
--- /dev/null
+++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h
@@ -0,0 +1,51 @@
+/** @file
+ The Header file of SerDes Module for LS1043A
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SOC_SERDES_H_
+#define SOC_SERDES_H_
+
+#ifdef CHASSIS2
+#include <Chassis2/LsSerDes.h>
+#endif
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+        /* SerDes 1 */
+  {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } },
+  {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
+  {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } },
+  {0x4558, {QsgmiiFm1A,  Pcie1, Pcie2, Sata } },
+  {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
+  {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
+  {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } },
+  {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
+  {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } },
+  {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
+  {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } },
+  {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } },
+  {0x9998, {Pcie1, Pcie2, Pcie3, Sata } },
+  {0x6058, {Pcie1, Pcie1, Pcie2, Sata } },
+  {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } },
+  {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
+  {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } },
+  {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
+  {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } },
+  {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
+  {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
+  {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
+  {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } },
+  {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }},
+  {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
+  {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+  SerDes1ConfigTbl
+};
+
+#endif /* SOC_SERDES_H_ */
diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
new file mode 100644
index 000000000000..99f6439d8f35
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
@@ -0,0 +1,136 @@
+/** @file
+*  Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+*  Copyright 2017-2019 NXP
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef NXP_CHASSIS_H_
+#define NXP_CHASSIS_H_
+
+#define TP_ITYP_AV_MASK            0x00000001  /* Initiator available */
+#define TP_ITYP_TYPE_MASK(x)       (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM           0x0
+#define TP_ITYP_TYPE_PPC           0x1
+#define TP_ITYP_TYPE_OTHER         0x2  /* StarCore DSP */
+#define TP_ITYP_TYPE_HA            0x3  /* HW Accelerator */
+#define TP_ITYP_THDS(x)            (((x) & 0x18) >> 3)  /* # threads */
+#define TP_ITYP_VERSION(x)         (((x) & 0xe0) >> 5)  /* Initiator Version */
+#define TP_CLUSTER_INIT_MASK       0x0000003f  /* initiator mask */
+#define TP_INIT_PER_CLUSTER        4
+
+#define TY_ITYP_VERSION_A7         0x1
+#define TY_ITYP_VERSION_A53        0x2
+#define TY_ITYP_VERSION_A57        0x3
+#define TY_ITYP_VERSION_A72        0x4
+
+#define CPU_TYPE_ENTRY(N, V, NC)   { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
+
+#define SVR_WO_E                    0xFFFFFE
+#define SVR_LS1043A                 0x879200
+#define SVR_LS1046A                 0x870700
+#define SVR_LS2088A                 0x870901
+
+#define SVR_MAJOR(svr)              (((svr) >> 4) & 0xf)
+#define SVR_MINOR(svr)              (((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr)            (((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr)         (!((svr >> 8) & 0x1))
+
+#define MHZ                         1000000
+
+typedef struct {
+  CHAR8  *Name;
+  UINT32 SocVer;
+  UINT32 NumCores;
+} CPU_TYPE;
+
+typedef struct {
+  UINTN CpuClk;  /* CPU clock in Hz! */
+  UINTN BusClk;
+  UINTN MemClk;
+  UINTN PciClk;
+  UINTN SdhcClk;
+} SOC_CLOCK_INFO;
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+  VOID
+  );
+
+/*
+ * Initialize Clock structure
+ */
+VOID
+ClockInit (
+  VOID
+  );
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+  VOID
+  );
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+  VOID
+  );
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+  VOID
+  );
+
+UINT32
+InitiatorType (
+  IN UINT32 Cluster,
+  IN UINTN InitId
+  );
+
+/*
+ *  Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+  VOID
+  );
+
+/*
+ *  Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+  VOID
+  );
+
+/*
+ * Return the type of initiator for core/hardware accelerator for given core index.
+ */
+UINTN
+QoriqCoreToType (
+  IN UINTN Core
+  );
+
+/*
+ *  Return the cluster of initiator for core/hardware accelerator for given core index.
+ */
+INT32
+QoriqCoreToCluster (
+  IN UINTN Core
+  );
+
+#endif /* NXP_CHASSIS_H_ */
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
new file mode 100644
index 000000000000..5dda6f8c2662
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -0,0 +1,498 @@
+/** @file
+  SoC specific Library containg functions to initialize various SoC components
+
+  Copyright 2017-2019 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#ifdef CHASSIS2
+#include <Chassis2/NxpSoc.h>
+#elif CHASSIS3
+#include <Chassis3/NxpSoc.h>
+#endif
+#include <Library/ArmSmcLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <DramInfo.h>
+#include "NxpChassis.h"
+
+/*
+ *  Structure to list available SOCs.
+ *  Name, Soc Version, Number of Cores
+ */
+STATIC CPU_TYPE mCpuTypeList[] = {
+  CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
+  CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
+  CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
+};
+
+UINT32
+EFIAPI
+GurRead (
+  IN  UINTN     Address
+  )
+{
+  if (FixedPcdGetBool (PcdGurBigEndian)) {
+    return SwapMmioRead32 (Address);
+  } else {
+    return MmioRead32 (Address);
+  }
+}
+
+/*
+ * Return the type of initiator (core or hardware accelerator)
+ */
+UINT32
+InitiatorType (
+  IN UINT32 Cluster,
+  IN UINTN  InitId
+  )
+{
+  CCSR_GUR *GurBase;
+  UINT32   Idx;
+  UINT32   Type;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
+  Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
+
+  if (Type & TP_ITYP_AV_MASK) {
+    return Type;
+  }
+
+  return 0;
+}
+
+/*
+ *  Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+  VOID
+  )
+{
+  CCSR_GUR  *GurBase;
+  UINTN     ClusterIndex;
+  UINTN     Count;
+  UINT32    Cluster;
+  UINT32    Type;
+  UINT32    Mask;
+  UINTN     InitiatorIndex;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  ClusterIndex = 0;
+  Count = 0;
+  Mask = 0;
+
+  do {
+    Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+    for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+      Type = InitiatorType (Cluster, InitiatorIndex);
+      if (Type) {
+        if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
+          Mask |= 1 << Count;
+        }
+        Count++;
+      }
+    }
+    ClusterIndex++;
+  } while (CHECK_CLUSTER (Cluster));
+
+  return Mask;
+}
+
+/*
+ *  Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+  VOID
+  )
+{
+  UINTN Count;
+  UINTN Num;
+
+  Count = 0;
+  Num = CpuMask ();
+
+  while (Num) {
+    Count += Num & 1;
+    Num >>= 1;
+  }
+
+  return Count;
+}
+
+/*
+ *  Return core's cluster
+ */
+INT32
+QoriqCoreToCluster (
+  IN UINTN Core
+  )
+{
+  CCSR_GUR  *GurBase;
+  UINTN     ClusterIndex;
+  UINTN     Count;
+  UINT32    Cluster;
+  UINT32    Type;
+  UINTN     InitiatorIndex;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  ClusterIndex = 0;
+  Count = 0;
+  do {
+    Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+    for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+      Type = InitiatorType (Cluster, InitiatorIndex);
+      if (Type) {
+        if (Count == Core) {
+          return ClusterIndex;
+        }
+        Count++;
+      }
+    }
+    ClusterIndex++;
+  } while (CHECK_CLUSTER (Cluster));
+
+  return -1;      // cannot identify the cluster
+}
+
+/*
+ *  Return the type of core i.e. A53, A57 etc of inputted
+ *  core number.
+ */
+UINTN
+QoriqCoreToType (
+  IN UINTN Core
+  )
+{
+  CCSR_GUR  *GurBase;
+  UINTN     ClusterIndex;
+  UINTN     Count;
+  UINT32    Cluster;
+  UINT32    Type;
+  UINTN     InitiatorIndex;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  ClusterIndex = 0;
+  Count = 0;
+
+  do {
+    Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+    for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+      Type = InitiatorType (Cluster, InitiatorIndex);
+      if (Type) {
+        if (Count == Core) {
+          return Type;
+        }
+        Count++;
+      }
+    }
+    ClusterIndex++;
+  } while (CHECK_CLUSTER (Cluster));
+
+  return EFI_NOT_FOUND;      /* cannot identify the cluster */
+}
+
+STATIC
+UINTN
+CpuMaskNext (
+  IN  UINTN  Cpu,
+  IN  UINTN  Mask
+  )
+{
+  for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
+
+  return Cpu;
+}
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+  VOID
+  )
+{
+  SYS_INFO SysInfo;
+  UINTN    CoreIndex;
+  UINTN    Core;
+  UINT32   Type;
+  UINT32   NumCpus;
+  UINT32   Mask;
+  CHAR8    *CoreName;
+
+  GetSysInfo (&SysInfo);
+  DEBUG ((DEBUG_INIT, "Clock Configuration:"));
+
+  NumCpus = CpuNumCores ();
+  Mask = CpuMask ();
+
+  for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
+       CoreIndex < NumCpus;
+       CoreIndex++, Core = CpuMaskNext(Core, Mask))
+  {
+    if (!(CoreIndex % 3)) {
+      DEBUG ((DEBUG_INIT, "\n      "));
+    }
+
+    Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
+    switch (Type) {
+      case TY_ITYP_VERSION_A7:
+        CoreName = "A7";
+        break;
+      case TY_ITYP_VERSION_A53:
+        CoreName = "A53";
+        break;
+      case TY_ITYP_VERSION_A57:
+        CoreName = "A57";
+        break;
+      case TY_ITYP_VERSION_A72:
+        CoreName = "A72";
+        break;
+      default:
+        CoreName = " Unknown Core ";
+    }
+    DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz  ",
+      Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
+  }
+
+  DEBUG ((DEBUG_INIT, "\n      Bus:      %-4d MHz  ", SysInfo.FreqSystemBus / MHZ));
+  DEBUG ((DEBUG_INIT, "DDR:      %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
+
+  if (SysInfo.FreqFman[0] != 0) {
+    DEBUG ((DEBUG_INIT, "\n      FMAN:     %-4d MHz  ",  SysInfo.FreqFman[0] / MHZ));
+  }
+
+  DEBUG ((DEBUG_INIT, "\n"));
+}
+
+/*
+ * Return system bus frequency
+ */
+UINT64
+GetBusFrequency (
+   VOID
+  )
+{
+  SYS_INFO SocSysInfo;
+
+  GetSysInfo (&SocSysInfo);
+
+  return SocSysInfo.FreqSystemBus;
+}
+
+/*
+ * Return SDXC bus frequency
+ */
+UINT64
+GetSdxcFrequency (
+   VOID
+  )
+{
+  SYS_INFO SocSysInfo;
+
+  GetSysInfo (&SocSysInfo);
+
+  return SocSysInfo.FreqSdhc;
+}
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+  VOID
+  )
+{
+  CHAR8    Buf[20];
+  CCSR_GUR *GurBase;
+  UINTN    Count;
+  //
+  // Svr : System Version Register
+  //
+  UINTN    Svr;
+  UINTN    Ver;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+  Svr = GurRead ((UINTN)&GurBase->Svr);
+  Ver = SVR_SOC_VER (Svr);
+
+  for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
+    if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+      AsciiStrCpyS (Buf, AsciiStrnLenS (mCpuTypeList[Count].Name, 7) + 1,
+        (CONST CHAR8 *)mCpuTypeList[Count].Name);
+
+      if (IS_E_PROCESSOR (Svr)) {
+        AsciiStrCatS (Buf,
+          (AsciiStrLen (Buf) + AsciiStrLen ((CONST CHAR8 *)"E") + 1),
+          (CONST CHAR8 *)"E");
+      }
+      break;
+    }
+  }
+
+  DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
+          Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
+
+  return;
+}
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+  VOID
+  )
+{
+  CCSR_GUR *Base;
+  UINTN    Count;
+
+  Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+  /*
+   * Display the RCW, so that no one gets confused as to what RCW
+   * we're actually using for this boot.
+   */
+
+  DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
+  for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) {
+    UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]);
+
+    if ((Count % 4) == 0) {
+      DEBUG ((DEBUG_INIT, "\n      %08x:", Count * 4));
+    }
+
+    DEBUG ((DEBUG_INIT, " %08x", Rcw));
+  }
+
+  DEBUG ((DEBUG_INIT, "\n"));
+}
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+  VOID
+  )
+{
+  UINT32 Value;
+
+  /* set pagesize as 64K and ssmu-500 in bypass mode */
+  Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
+  MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
+
+  Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+  MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
+
+  Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+  MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
+}
+
+/*
+ * Return current Soc Name form mCpuTypeList
+ */
+CHAR8 *
+GetSocName (
+  VOID
+  )
+{
+  UINT8     Count;
+  UINTN     Svr;
+  UINTN     Ver;
+  CCSR_GUR  *GurBase;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+  Svr = GurRead ((UINTN)&GurBase->Svr);
+  Ver = SVR_SOC_VER (Svr);
+
+  for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
+    if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+      return (CHAR8 *)mCpuTypeList[Count].Name;
+    }
+  }
+
+  return NULL;
+}
+
+UINTN
+GetDramSize (
+  IN VOID
+  )
+{
+  ARM_SMC_ARGS  ArmSmcArgs;
+
+  ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+  ArmSmcArgs.Arg1 = -1;
+
+  ArmCallSmc (&ArmSmcArgs);
+
+  if (ArmSmcArgs.Arg0) {
+    return 0;
+  } else {
+    return ArmSmcArgs.Arg1;
+  }
+}
+
+EFI_STATUS
+GetDramBankInfo (
+  IN OUT DRAM_INFO *DramInfo
+  )
+{
+  ARM_SMC_ARGS  ArmSmcArgs;
+  UINT32        I;
+  UINTN         DramSize;
+
+  DramSize = GetDramSize ();
+  DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
+
+  // Ensure DramSize has been set
+  ASSERT (DramSize != 0);
+
+  I = 0;
+
+  do {
+    ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+    ArmSmcArgs.Arg1 = I;
+
+    ArmCallSmc (&ArmSmcArgs);
+    if (ArmSmcArgs.Arg0) {
+      if (I > 0) {
+        break;
+      } else {
+        ASSERT (ArmSmcArgs.Arg0 == 0);
+      }
+    }
+
+    DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
+    DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
+
+    DramSize -= DramInfo->DramRegion[I].Size;
+
+    DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
+      I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size));
+
+    I++;
+  } while (DramSize);
+
+  DramInfo->NumOfDrams = I;
+
+  DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams));
+
+  return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
new file mode 100644
index 000000000000..bfb8b8cb339a
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -0,0 +1,162 @@
+/** @Soc.c
+  SoC specific Library containg functions to initialize various SoC components
+
+  Copyright 2017-2019 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <NxpChassis.h>
+#include <Chassis2/NxpSoc.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+/**
+  Calculate the frequency of various controllers and
+  populate the passed structure with frequuencies.
+
+  @param  PtrSysInfo            Input structure to populate with
+                                frequencies.
+**/
+VOID
+GetSysInfo (
+  OUT SYS_INFO *PtrSysInfo
+  )
+{
+  CCSR_GUR     *GurBase;
+  CCSR_CLOCK   *ClkBase;
+  UINTN        CpuIndex;
+  UINT32       TempRcw;
+  UINT32       CPllSel;
+  UINT32       CplxPll;
+  CONST UINT8  CoreCplxPll[8] = {
+    [0] = 0,    /* CC1 PPL / 1 */
+    [1] = 0,    /* CC1 PPL / 2 */
+    [4] = 1,    /* CC2 PPL / 1 */
+    [5] = 1,    /* CC2 PPL / 2 */
+  };
+
+  CONST UINT8  CoreCplxPllDivisor[8] = {
+    [0] = 1,    /* CC1 PPL / 1 */
+    [1] = 2,    /* CC1 PPL / 2 */
+    [4] = 1,    /* CC2 PPL / 1 */
+    [5] = 2,    /* CC2 PPL / 2 */
+  };
+
+  UINTN        PllCount;
+  UINTN        FreqCPll[NUM_CC_PLLS];
+  UINTN        PllRatio[NUM_CC_PLLS];
+  UINTN        SysClk;
+
+  GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
+  SysClk = CLK_FREQ;
+
+  SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
+
+  PtrSysInfo->FreqSystemBus = SysClk;
+  PtrSysInfo->FreqDdrBus = SysClk;
+
+  //
+  // selects the platform clock:SYSCLK ratio and calculate
+  // system frequency
+  //
+  PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+                CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+                CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+  //
+  // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
+  //
+  PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+                CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+                CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+
+  for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
+    PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
+    if (PllRatio[PllCount] > 4) {
+      FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
+    } else {
+      FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
+    }
+  }
+
+  //
+  // Calculate Core frequency
+  //
+  for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
+    CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
+    CplxPll = CoreCplxPll[CPllSel];
+
+    PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
+  }
+
+  //
+  // Calculate FMAN frequency
+  //
+  TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
+  switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+  case 2:
+    PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
+    break;
+  case 3:
+    PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
+    break;
+  case 4:
+    PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
+    break;
+  case 5:
+    PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
+    break;
+  case 6:
+    PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
+    break;
+  case 7:
+    PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
+    break;
+  default:
+    DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
+    break;
+  }
+  PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+  PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+}
+
+/**
+  Function to initialize SoC specific constructs
+  CPU Info
+  SoC Personality
+  Board Personality
+  RCW prints
+ **/
+VOID
+SocInit (
+  VOID
+  )
+{
+  SmmuInit ();
+
+  //
+  // Early init serial Port to get board information.
+  //
+  SerialPortInitialize ();
+  DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
+          (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
+
+  PrintCpuInfo ();
+
+  //
+  // Print Reset control Word
+  //
+  PrintRCW ();
+  PrintSoc ();
+
+  return;
+}
diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
new file mode 100644
index 000000000000..b9909d922138
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/SerDes.c
@@ -0,0 +1,268 @@
+/** SerDes.c
+  Provides the basic interfaces for SerDes Module
+
+  Copyright 2017-2019 NXP
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef CHASSIS2
+#include <Chassis2/LsSerDes.h>
+#include <Chassis2/NxpSoc.h>
+#elif CHASSIS3
+#include <Chassis3/LsSerDes.h>
+#include <Chassis3/NxpSoc.h>
+#endif
+#include <Library/DebugLib.h>
+#include <SocSerDes.h>
+#include <Uefi.h>
+
+/**
+  Function to get serdes Lane protocol corresponding to
+  serdes protocol.
+
+  @param  SerDes    Serdes number.
+  @param  Cfg       Serdes Protocol.
+  @param  Lane      Serdes Lane number.
+
+  @return           Serdes Lane protocol.
+
+**/
+STATIC
+SERDES_PROTOCOL
+GetSerDesPrtcl (
+  IN  INTN          SerDes,
+  IN  INTN          Cfg,
+  IN  INTN          Lane
+  )
+{
+  SERDES_CONFIG     *Config;
+
+  if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+    return 0;
+  }
+
+  Config = SerDesConfigTbl[SerDes];
+  while (Config->Protocol) {
+    if (Config->Protocol == Cfg) {
+      return Config->SrdsLane[Lane];
+    }
+    Config++;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Function to check if inputted protocol is a valid serdes protocol.
+
+  @param  SerDes                   Serdes number.
+  @param  Prtcl                    Serdes Protocol to be verified.
+
+  @return EFI_INVALID_PARAMETER    Input parameter in invalid.
+  @return EFI_NOT_FOUND            Serdes Protocol not a valid protocol.
+  @return EFI_SUCCESS              Serdes Protocol is a valid protocol.
+
+**/
+STATIC
+EFI_STATUS
+CheckSerDesPrtclValid (
+  IN  INTN      SerDes,
+  IN  UINT32    Prtcl
+  )
+{
+  SERDES_CONFIG *Config;
+  INTN          Cnt;
+
+  if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Config = SerDesConfigTbl[SerDes];
+  while (Config->Protocol) {
+    if (Config->Protocol == Prtcl) {
+      DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
+      break;
+    }
+    Config++;
+  }
+
+  if (!Config->Protocol) {
+    return EFI_NOT_FOUND;
+  }
+
+  for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
+    if (Config->SrdsLane[Cnt] != None) {
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
+
+/**
+  Function to fill serdes map information.
+
+  @param  Srds                  Serdes number.
+  @param  SerdesProtocolMask    Serdes Protocol Mask.
+  @param  SerdesProtocolShift   Serdes Protocol shift value.
+  @param  SerDesPrtclMap        Pointer to Serdes Protocol map.
+
+**/
+STATIC
+VOID
+LSSerDesMap (
+  IN  UINT32                    Srds,
+  IN  UINT32                    SerdesProtocolMask,
+  IN  UINT32                    SerdesProtocolShift,
+  OUT UINT64                    *SerDesPrtclMap
+  )
+{
+  CCSR_GUR                      *Gur;
+  UINT32                        SrdsProt;
+  INTN                          Lane;
+  UINT32                        Flag;
+
+  Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+  *SerDesPrtclMap = 0x0;
+  Flag = 0;
+
+  SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+  SrdsProt >>= SerdesProtocolShift;
+
+  DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
+          Srds + 1, SrdsProt, SrdsProt));
+
+  if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
+    DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
+            Srds + 1, SrdsProt));
+    Flag++;
+  }
+
+  for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+    SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+    if (LanePrtcl >= SerdesPrtclCount) {
+      DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+      Flag++;
+    } else {
+      *SerDesPrtclMap |= (1u << LanePrtcl);
+    }
+  }
+
+  if (Flag) {
+    DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
+  } else {
+    DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
+  }
+}
+
+/**
+  Get lane protocol on provided serdes lane and execute callback function.
+
+  @param  Srds                    Serdes number.
+  @param  SerdesProtocolMask      Mask to get Serdes Protocol for Srds
+  @param  SerdesProtocolShift     Shift value to get Serdes Protocol for Srds.
+  @param  SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+  @param  Arg                     Pointer to Arguments to be passed to callback function.
+
+**/
+STATIC
+VOID
+SerDesInstanceProbeLanes (
+  IN  UINT32                      Srds,
+  IN  UINT32                      SerdesProtocolMask,
+  IN  UINT32                      SerdesProtocolShift,
+  IN  SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+  IN  VOID                        *Arg
+  )
+{
+
+  CCSR_GUR                        *Gur;
+  UINT32                          SrdsProt;
+  INTN                            Lane;
+
+  Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
+
+  SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+  SrdsProt >>= SerdesProtocolShift;
+
+  /*
+   * Invoke callback for all lanes in the SerDes instance:
+   */
+  for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+    SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+    if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) {
+      DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+    } else if (LanePrtcl != None) {
+      SerDesLaneProbeCallback (LanePrtcl, Arg);
+    }
+  }
+}
+
+/**
+  Probe all serdes lanes for lane protocol and execute provided callback function.
+
+  @param  SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+  @param  Arg                     Pointer to Arguments to be passed to callback function.
+
+**/
+VOID
+SerDesProbeLanes (
+  IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+  IN VOID                        *Arg
+  )
+{
+  SerDesInstanceProbeLanes (Srds1,
+                            RCWSR_SRDS1_PRTCL_MASK,
+                            RCWSR_SRDS1_PRTCL_SHIFT,
+                            SerDesLaneProbeCallback,
+                            Arg);
+
+  if (PcdGetBool (PcdSerdes2Enabled)) {
+   SerDesInstanceProbeLanes (Srds2,
+                             RCWSR_SRDS2_PRTCL_MASK,
+                             RCWSR_SRDS2_PRTCL_SHIFT,
+                             SerDesLaneProbeCallback,
+                             Arg);
+  }
+}
+
+/**
+  Function to return Serdes protocol map for all serdes available on board.
+
+  @param  SerDesPrtclMap   Pointer to Serdes protocl map.
+
+**/
+VOID
+GetSerdesProtocolMaps (
+  OUT UINT64               *SerDesPrtclMap
+  )
+{
+  LSSerDesMap (Srds1,
+               RCWSR_SRDS1_PRTCL_MASK,
+               RCWSR_SRDS1_PRTCL_SHIFT,
+               SerDesPrtclMap);
+
+  if (PcdGetBool (PcdSerdes2Enabled)) {
+    LSSerDesMap (Srds2,
+                 RCWSR_SRDS2_PRTCL_MASK,
+                 RCWSR_SRDS2_PRTCL_SHIFT,
+                 SerDesPrtclMap);
+  }
+
+}
+
+BOOLEAN
+IsSerDesLaneProtocolConfigured (
+  IN UINT64          SerDesPrtclMap,
+  IN SERDES_PROTOCOL Device
+  )
+{
+  if ((Device >= SerdesPrtclCount) || (Device < None)) {
+    ASSERT ((Device > None) && (Device < SerdesPrtclCount));
+    DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
+  }
+
+  return (SerDesPrtclMap & (1u << Device)) != 0 ;
+}
-- 
1.9.1