From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (NAM11-BN8-obe.outbound.protection.outlook.com [40.107.236.77]) by mx.groups.io with SMTP id smtpd.web12.372.1582659641066393603 for ; Tue, 25 Feb 2020 11:40:41 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@amdcloud.onmicrosoft.com header.s=selector2-amdcloud-onmicrosoft-com header.b=3odflvyp; spf=none, err=SPF record not found (domain: amd.com, ip: 40.107.236.77, mailfrom: leo.duran@amd.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QEqz0ofuWEhpDvnB+VQOdIn8XHprHVRMvMRb16xxSOQACvzETz4J5cdWaVFGUQcFrrN8G4z3Bz65nynjo2GGVUEkRUGaK/+qxxr/Mcm2Y9wo5rXtDp3V6kOaX5hZ6oKHSmxHpG/ilHU6IXkrraTJOtjoe57f12liLx1ciENhAyo7NBqlHzyJKOl6SasAWQKw+qCp8XZnLjEPffXkYD3csbWciyMbQiyJSFth0wftBtIXsnuKzE+k3nhXsxVzrDy1X/20/2bMgKXjDk//d92cXV1ZfvkBFuLcF2Bj9XV0Ok1+TupSicW7H5DgsauOeEEkpkAXVuZ0+Y70CDFQVRfzjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FyNiL3zTHcEYmjL8UI8mNHAGWqP19yQZJXplISMFsZo=; b=ARsvg3PUN89Bdg1k4QOZqPc14eHgmuEEBqlYNX7yJSjwcOntEDxgs8oVnPvXDfua4q6zSjFdaG69fSRk822NmQEG1W2eUDFM2u4bv9ng0KHAA+36vUAbZYVc9eAvv7tnDux3hOFJTXoJ9KTmzzhrNl8GCb2VygDYfshcpSafxM0hOUQb6yhIx8j4RLCAAb0+JHVFk5cxcb3xuubxTKqgE0QIcRBCwskK5g3OAif0Tlz6R3YDCwhbIep+9zZEWUFkySX9P0zQdzvabtCK7/QOQeSG7ev/19IzncIhY5YKNHGKeXlmNZDqY2Mq3iJAbKOuMcCwmC/U+soyG+np9LF58g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FyNiL3zTHcEYmjL8UI8mNHAGWqP19yQZJXplISMFsZo=; b=3odflvypR5wfcnoUzZp9Zeh2LNS0r8IJdiFtmbDRWHoz5TkTSSp5LaYE9JQucaqP0w5mohTN3BmV4Vye0itwzOup+O7wzUTnsdNt+wogvI3pOZROOHe8CdLcbAfDa+tQKXqogVIlqiqN4E/VGZ7q/Uj9XgDFN8U6SR04lygoT/I= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=leo.duran@amd.com; Received: from BN6PR12MB1922.namprd12.prod.outlook.com (2603:10b6:404:106::14) by BN6PR12MB1410.namprd12.prod.outlook.com (2603:10b6:404:18::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2750.17; Tue, 25 Feb 2020 19:40:39 +0000 Received: from BN6PR12MB1922.namprd12.prod.outlook.com ([fe80::d931:1942:a6b5:d74c]) by BN6PR12MB1922.namprd12.prod.outlook.com ([fe80::d931:1942:a6b5:d74c%7]) with mapi id 15.20.2750.021; Tue, 25 Feb 2020 19:40:39 +0000 From: Leo Duran To: devel@edk2.groups.io Cc: Leo Duran , Eric Dong , Ray Ni , Laszlo Ersek Subject: [PATCH 2/2] UefiCpuPkg: MpInitLib: Exclude code no pertinent to AMD processors. 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Specifically, the PlatformId MSR and embedded Microcode patches are not relevant on AMD-based platforms. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Leo Duran --- UefiCpuPkg/Library/MpInitLib/Microcode.c | 17 +++++++++++++++-- UefiCpuPkg/Library/MpInitLib/MpLib.c | 11 +++++++++-- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/MpInitLib/Microcode.c index 1562959..750681d 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -2,6 +2,8 @@ Implementation of loading microcode on processors. Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, AMD Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -97,9 +99,13 @@ MicrocodeDetect ( UINT32 ThreadId; BOOLEAN IsBspCallIn; - if (CpuMpData->MicrocodePatchRegionSize == 0) { + // + // NOTE: Embedded Microcode patches are not relevant on AMD platforms. + // + if (CpuMpData->MicrocodePatchRegionSize == 0 || + StandardSignatureIsAuthenticAMD ()) { // - // There is no microcode patches + // There are no microcode patches // return; } @@ -350,6 +356,13 @@ IsProcessorMatchedMicrocodePatch ( UINTN Index; CPU_AP_DATA *CpuData; + // + // NOTE: PlatformId or embedded Microcode patches are not relevant on AMD platforms. + // + if (StandardSignatureIsAuthenticAMD ()) { + return FALSE; + } + for (Index = 0; Index < CpuMpData->CpuCount; Index++) { CpuData = &CpuMpData->CpuData[Index]; if ((ProcessorSignature == CpuData->ProcessorSignature) && diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index d0fbc17..290e7bf 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -2,6 +2,8 @@ CPU MP Initialize Library common functions. Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, AMD Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -564,8 +566,13 @@ InitializeApData ( CpuMpData->CpuData[ProcessorNumber].Waiting = FALSE; CpuMpData->CpuData[ProcessorNumber].CpuHealthy = (BistData == 0) ? TRUE : FALSE; - PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); - CpuMpData->CpuData[ProcessorNumber].PlatformId = (UINT8) PlatformIdMsr.Bits.PlatformId; + // + // NOTE: PlatformId is not relevant on AMD platforms. + // + if (!StandardSignatureIsAuthenticAMD ()) { + PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + CpuMpData->CpuData[ProcessorNumber].PlatformId = (UINT8)PlatformIdMsr.Bits.PlatformId; + } AsmCpuid ( CPUID_VERSION_INFO, -- 2.7.4