* [edk2-platforms: PATCH 0/3] Marvell UTMI fixes
@ 2020-05-12 18:59 Marcin Wojtas
2020-05-12 18:59 ` [edk2-platforms: PATCH 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings Marcin Wojtas
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Marcin Wojtas @ 2020-05-12 18:59 UTC (permalink / raw)
To: devel; +Cc: ard.biesheuvel, leif, mw, jsd, jaz, kostap
Hi,
This patchset introduces fixes to the UTMI part of the
XHCI interfaces found in Armada/CN913x SoC families,
as well as improves the analog PHY settings.
The details can be found in the commit logs.
The patches are available in the public git branch:
https://github.com/Semihalf/edk2-platforms/commits/utmi-upstream-r20200512
I'm looking forward to the comments and remarks.
Best regards,
Marcin
Marcin Wojtas (3):
Marvell/Library: UtmiLib: update USB2.0 analog settings
Marvell/Library: UtmiLib: fix pll initialization for the second port
Marvell/Library: UtmiLib: Fix USB mux configuration
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 3 +-
Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 1 +
Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 24 +++++++++---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 1 +
Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 41 ++++++++++++++------
5 files changed, 52 insertions(+), 18 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread* [edk2-platforms: PATCH 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings 2020-05-12 18:59 [edk2-platforms: PATCH 0/3] Marvell UTMI fixes Marcin Wojtas @ 2020-05-12 18:59 ` Marcin Wojtas 2020-05-13 13:41 ` Leif Lindholm 2020-05-12 18:59 ` [edk2-platforms: PATCH 2/3] Marvell/Library: UtmiLib: fix pll initialization for the second port Marcin Wojtas 2020-05-12 18:59 ` [edk2-platforms: PATCH 3/3] Marvell/Library: UtmiLib: Fix USB mux configuration Marcin Wojtas 2 siblings, 1 reply; 7+ messages in thread From: Marcin Wojtas @ 2020-05-12 18:59 UTC (permalink / raw) To: devel; +Cc: ard.biesheuvel, leif, mw, jsd, jaz, kostap This patch introduce following modifications, allowing to overcome the instabilities observed with certain USB2.0 endpoints: * Add additional step which enables the Impedance and PLL calibration. * Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. * Update LS TX driver strength coarse and fine adjustment values. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 10 +++++++- Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 26 ++++++++++++++------ 2 files changed, 27 insertions(+), 9 deletions(-) diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h index 20e3133..8659110 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h @@ -44,6 +44,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define UTMI_CALIB_CTRL_REG 0x8 #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) +#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13 +#define UTMI_CALIB_CTRL_IMPCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET) +#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22 +#define UTMI_CALIB_CTRL_PLLCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET) #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 @@ -54,8 +58,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) +#define UTMI_TX_CH_CTRL_AMP_OFFSET 20 +#define UTMI_TX_CH_CTRL_AMP_MASK (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET) #define UTMI_RX_CH_CTRL0_REG 0x14 +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET) #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 #define UTMI_RX_CH_CTRL0_SQ_DET_MASK (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 @@ -63,7 +71,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define UTMI_RX_CH_CTRL1_REG 0x18 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 -#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c index 3881ebd..60ea06e 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c @@ -117,24 +117,34 @@ UtmiPhyConfig ( RegSet (UtmiBaseAddr + UTMI_PLL_CTRL_REG, Data, Mask); /* Impedance Calibration Threshold Setting */ - RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, - 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, - UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); + Mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK; + Data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET; + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); + + /* Start Impedance and PLL Calibration */ + Mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK; + Data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); + Mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK; + Data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); /* Set LS TX driver strength coarse control */ - Mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; - Data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; - /* Set LS TX driver fine adjustment */ + Mask = UTMI_TX_CH_CTRL_AMP_MASK; + Data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; Mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; Data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; + Mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; + Data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); /* Enable SQ */ Mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; - Data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; + Data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; /* Enable analog squelch detect */ Mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; - Data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; + Data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; + Mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; + Data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; RegSet (UtmiBaseAddr + UTMI_RX_CH_CTRL0_REG, Data, Mask); /* Set External squelch calibration number */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [edk2-platforms: PATCH 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings 2020-05-12 18:59 ` [edk2-platforms: PATCH 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings Marcin Wojtas @ 2020-05-13 13:41 ` Leif Lindholm 2020-05-13 13:55 ` Marcin Wojtas 0 siblings, 1 reply; 7+ messages in thread From: Leif Lindholm @ 2020-05-13 13:41 UTC (permalink / raw) To: Marcin Wojtas; +Cc: devel, ard.biesheuvel, jsd, jaz, kostap On Tue, May 12, 2020 at 20:59:29 +0200, Marcin Wojtas wrote: > This patch introduce following modifications, allowing to > overcome the instabilities observed with certain USB2.0 endpoints: > * Add additional step which enables the Impedance and PLL calibration. > * Enable old squelch detector instead of the new analog squelch detector > circuit and update host disconnect threshold value. > * Update LS TX driver strength coarse and fine adjustment values. > > Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > --- > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 10 +++++++- > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 26 ++++++++++++++------ > 2 files changed, 27 insertions(+), 9 deletions(-) > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > index 20e3133..8659110 100644 > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > @@ -44,6 +44,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #define UTMI_CALIB_CTRL_REG 0x8 > #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 > #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) > +#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13 > +#define UTMI_CALIB_CTRL_IMPCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET) > +#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22 > +#define UTMI_CALIB_CTRL_PLLCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET) > #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 > #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) > #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 > @@ -54,8 +58,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) > +#define UTMI_TX_CH_CTRL_AMP_OFFSET 20 > +#define UTMI_TX_CH_CTRL_AMP_MASK (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET) > > #define UTMI_RX_CH_CTRL0_REG 0x14 > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET) > #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 > #define UTMI_RX_CH_CTRL0_SQ_DET_MASK (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) > #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 > @@ -63,7 +71,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #define UTMI_RX_CH_CTRL1_REG 0x18 > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 > -#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) > +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > index 3881ebd..60ea06e 100644 > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > @@ -117,24 +117,34 @@ UtmiPhyConfig ( > RegSet (UtmiBaseAddr + UTMI_PLL_CTRL_REG, Data, Mask); > > /* Impedance Calibration Threshold Setting */ > - RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, > - 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > - UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); > + Mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK; > + Data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET; > + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); > + > + /* Start Impedance and PLL Calibration */ > + Mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK; > + Data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); > + Mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK; > + Data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); > + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); > > /* Set LS TX driver strength coarse control */ > - Mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > - Data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > - /* Set LS TX driver fine adjustment */ > + Mask = UTMI_TX_CH_CTRL_AMP_MASK; > + Data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; > Mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; > Data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; > + Mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > + Data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); The above looks a bit more chaotic than necessary, partly because what looks like spuriously moving the existing assignment around and deleting a comment Is there a rationale behind that? I.e., the following would appear equivalent: /* Set LS TX driver strength coarse control */ Mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; Data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; + Mask |= UTMI_TX_CH_CTRL_AMP_MASK; + Data |= 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; /* Set LS TX driver fine adjustment */ Mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; Data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); / Leif > > /* Enable SQ */ > Mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; > - Data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > + Data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > /* Enable analog squelch detect */ > Mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; > - Data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > + Data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > + Mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; > + Data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; > RegSet (UtmiBaseAddr + UTMI_RX_CH_CTRL0_REG, Data, Mask); > > /* Set External squelch calibration number */ > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [edk2-platforms: PATCH 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings 2020-05-13 13:41 ` Leif Lindholm @ 2020-05-13 13:55 ` Marcin Wojtas 2020-05-13 14:27 ` Leif Lindholm 0 siblings, 1 reply; 7+ messages in thread From: Marcin Wojtas @ 2020-05-13 13:55 UTC (permalink / raw) To: Leif Lindholm Cc: edk2-devel-groups-io, ard.biesheuvel, jsd@semihalf.com, Grzegorz Jaszczyk, Kostya Porotchkin Hi Leif, śr., 13 maj 2020 o 15:41 Leif Lindholm <leif@nuviainc.com> napisał(a): > > On Tue, May 12, 2020 at 20:59:29 +0200, Marcin Wojtas wrote: > > This patch introduce following modifications, allowing to > > overcome the instabilities observed with certain USB2.0 endpoints: > > * Add additional step which enables the Impedance and PLL calibration. > > * Enable old squelch detector instead of the new analog squelch detector > > circuit and update host disconnect threshold value. > > * Update LS TX driver strength coarse and fine adjustment values. > > > > Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > > --- > > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 10 +++++++- > > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 26 ++++++++++++++------ > > 2 files changed, 27 insertions(+), 9 deletions(-) > > > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > index 20e3133..8659110 100644 > > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > @@ -44,6 +44,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #define UTMI_CALIB_CTRL_REG 0x8 > > #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 > > #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) > > +#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13 > > +#define UTMI_CALIB_CTRL_IMPCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET) > > +#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22 > > +#define UTMI_CALIB_CTRL_PLLCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET) > > #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 > > #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) > > #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 > > @@ -54,8 +58,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) > > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 > > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) > > +#define UTMI_TX_CH_CTRL_AMP_OFFSET 20 > > +#define UTMI_TX_CH_CTRL_AMP_MASK (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET) > > > > #define UTMI_RX_CH_CTRL0_REG 0x14 > > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 > > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET) > > #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 > > #define UTMI_RX_CH_CTRL0_SQ_DET_MASK (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) > > #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 > > @@ -63,7 +71,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > > #define UTMI_RX_CH_CTRL1_REG 0x18 > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 > > -#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) > > +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) > > > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > index 3881ebd..60ea06e 100644 > > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > @@ -117,24 +117,34 @@ UtmiPhyConfig ( > > RegSet (UtmiBaseAddr + UTMI_PLL_CTRL_REG, Data, Mask); > > > > /* Impedance Calibration Threshold Setting */ > > - RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, > > - 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > > - UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); > > + Mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK; > > + Data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET; > > + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); > > + > > + /* Start Impedance and PLL Calibration */ > > + Mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK; > > + Data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); > > + Mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK; > > + Data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); > > + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); > > > > /* Set LS TX driver strength coarse control */ > > - Mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > > - Data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > > - /* Set LS TX driver fine adjustment */ > > + Mask = UTMI_TX_CH_CTRL_AMP_MASK; > > + Data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; > > Mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; > > Data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; > > + Mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > > + Data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > > RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); > > The above looks a bit more chaotic than necessary, partly because what > looks like spuriously moving the existing assignment around and > deleting a comment Is there a rationale behind that? > > I.e., the following would appear equivalent: > > /* Set LS TX driver strength coarse control */ > Mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > Data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > + Mask |= UTMI_TX_CH_CTRL_AMP_MASK; > + Data |= 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; > /* Set LS TX driver fine adjustment */ > Mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; > Data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; > RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); > Right, I'll recheck and simplify the diff as much as possible in this aspect. Best regards, Marcin > / > Leif > > > > > /* Enable SQ */ > > Mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; > > - Data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > > + Data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > > /* Enable analog squelch detect */ > > Mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; > > - Data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > > + Data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > > + Mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; > > + Data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; > > RegSet (UtmiBaseAddr + UTMI_RX_CH_CTRL0_REG, Data, Mask); > > > > /* Set External squelch calibration number */ > > -- > > 2.7.4 > > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [edk2-platforms: PATCH 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings 2020-05-13 13:55 ` Marcin Wojtas @ 2020-05-13 14:27 ` Leif Lindholm 0 siblings, 0 replies; 7+ messages in thread From: Leif Lindholm @ 2020-05-13 14:27 UTC (permalink / raw) To: Marcin Wojtas Cc: edk2-devel-groups-io, ard.biesheuvel, jsd@semihalf.com, Grzegorz Jaszczyk, Kostya Porotchkin On Wed, May 13, 2020 at 15:55:47 +0200, Marcin Wojtas wrote: > Hi Leif, > > śr., 13 maj 2020 o 15:41 Leif Lindholm <leif@nuviainc.com> napisał(a): > > > > On Tue, May 12, 2020 at 20:59:29 +0200, Marcin Wojtas wrote: > > > This patch introduce following modifications, allowing to > > > overcome the instabilities observed with certain USB2.0 endpoints: > > > * Add additional step which enables the Impedance and PLL calibration. > > > * Enable old squelch detector instead of the new analog squelch detector > > > circuit and update host disconnect threshold value. > > > * Update LS TX driver strength coarse and fine adjustment values. > > > > > > Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> > > > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > > > --- > > > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 10 +++++++- > > > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 26 ++++++++++++++------ > > > 2 files changed, 27 insertions(+), 9 deletions(-) > > > > > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > > index 20e3133..8659110 100644 > > > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > > @@ -44,6 +44,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > #define UTMI_CALIB_CTRL_REG 0x8 > > > #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 > > > #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) > > > +#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13 > > > +#define UTMI_CALIB_CTRL_IMPCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET) > > > +#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22 > > > +#define UTMI_CALIB_CTRL_PLLCAL_START_MASK (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET) > > > #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 > > > #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) > > > #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 > > > @@ -54,8 +58,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) > > > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 > > > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) > > > +#define UTMI_TX_CH_CTRL_AMP_OFFSET 20 > > > +#define UTMI_TX_CH_CTRL_AMP_MASK (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET) > > > > > > #define UTMI_RX_CH_CTRL0_REG 0x14 > > > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 > > > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET) > > > #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 > > > #define UTMI_RX_CH_CTRL0_SQ_DET_MASK (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) > > > #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 > > > @@ -63,7 +71,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > #define UTMI_RX_CH_CTRL1_REG 0x18 > > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 > > > -#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) > > > +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) > > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 > > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) > > > > > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > > index 3881ebd..60ea06e 100644 > > > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > > @@ -117,24 +117,34 @@ UtmiPhyConfig ( > > > RegSet (UtmiBaseAddr + UTMI_PLL_CTRL_REG, Data, Mask); > > > > > > /* Impedance Calibration Threshold Setting */ > > > - RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, > > > - 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > > > - UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); > > > + Mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK; > > > + Data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET; > > > + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); > > > + > > > + /* Start Impedance and PLL Calibration */ > > > + Mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK; > > > + Data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); > > > + Mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK; > > > + Data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); > > > + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); > > > > > > /* Set LS TX driver strength coarse control */ > > > - Mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > > > - Data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > > > - /* Set LS TX driver fine adjustment */ > > > + Mask = UTMI_TX_CH_CTRL_AMP_MASK; > > > + Data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; > > > Mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; > > > Data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; > > > + Mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > > > + Data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > > > RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); > > > > The above looks a bit more chaotic than necessary, partly because what > > looks like spuriously moving the existing assignment around and > > deleting a comment Is there a rationale behind that? > > > > I.e., the following would appear equivalent: > > > > /* Set LS TX driver strength coarse control */ > > Mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > > Data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > > + Mask |= UTMI_TX_CH_CTRL_AMP_MASK; > > + Data |= 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; > > /* Set LS TX driver fine adjustment */ > > Mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; > > Data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; > > RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); > > > > Right, I'll recheck and simplify the diff as much as possible in this aspect. Thanks. For clarity, I have no issue with 2-3/3, so you can just resubmit this one after rework. Regards, Leif > > Best regards, > Marcin > > > / > > Leif > > > > > > > > /* Enable SQ */ > > > Mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; > > > - Data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > > > + Data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > > > /* Enable analog squelch detect */ > > > Mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; > > > - Data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > > > + Data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > > > + Mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; > > > + Data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; > > > RegSet (UtmiBaseAddr + UTMI_RX_CH_CTRL0_REG, Data, Mask); > > > > > > /* Set External squelch calibration number */ > > > -- > > > 2.7.4 > > > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [edk2-platforms: PATCH 2/3] Marvell/Library: UtmiLib: fix pll initialization for the second port 2020-05-12 18:59 [edk2-platforms: PATCH 0/3] Marvell UTMI fixes Marcin Wojtas 2020-05-12 18:59 ` [edk2-platforms: PATCH 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings Marcin Wojtas @ 2020-05-12 18:59 ` Marcin Wojtas 2020-05-12 18:59 ` [edk2-platforms: PATCH 3/3] Marvell/Library: UtmiLib: Fix USB mux configuration Marcin Wojtas 2 siblings, 0 replies; 7+ messages in thread From: Marcin Wojtas @ 2020-05-12 18:59 UTC (permalink / raw) To: devel; +Cc: ard.biesheuvel, leif, mw, jsd, jaz, kostap According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This fixes issues in scenarios when only UTMI port1 was in use, which resulted with lack of correct PLL initialization. On the occasion add relevant comments, describing the register groups in the header file. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 3 ++- Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 1 + Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 14 +++++++++----- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 1 + Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 18 +++++++++++++----- 5 files changed, 26 insertions(+), 11 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h index 265b4f4..345ca0a 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h @@ -99,7 +99,8 @@ // #define MV_SOC_UTMI_PER_CP_COUNT 2 #define MV_SOC_UTMI_ID(Utmi) (Utmi) -#define MV_SOC_UTMI_BASE(Utmi) (0x580000 + ((Utmi) * 0x1000)) +#define MV_SOC_UTMI_BASE(Utmi) (0x58000C + ((Utmi) * 0x1000)) +#define MV_SOC_UTMI_PLL_BASE 0x580000 #define MV_SOC_UTMI_CFG_BASE 0x440440 #define MV_SOC_UTMI_USB_CFG_BASE 0x440420 diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h index da7a41e..0d568ad 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -226,6 +226,7 @@ ArmadaSoCDescPp2Get ( typedef struct { UINT8 UtmiPhyId; UINTN UtmiBaseAddress; + UINTN UtmiPllAddress; UINTN UtmiConfigAddress; UINTN UsbConfigAddress; } MV_SOC_UTMI_DESC; diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h index 8659110..11421a9 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h @@ -21,6 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Protocol/BoardDesc.h> +/* USB Configuration register */ #define UTMI_USB_CFG_DEVICE_EN_OFFSET 0 #define UTMI_USB_CFG_DEVICE_EN_MASK (0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET) #define UTMI_USB_CFG_DEVICE_MUX_OFFSET 1 @@ -28,9 +29,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define UTMI_USB_CFG_PLL_OFFSET 25 #define UTMI_USB_CFG_PLL_MASK (0x1 << UTMI_USB_CFG_PLL_OFFSET) +/* UTMI Configuration register */ #define UTMI_PHY_CFG_PU_OFFSET 5 #define UTMI_PHY_CFG_PU_MASK (0x1 << UTMI_PHY_CFG_PU_OFFSET) +/* UTMI PLL registers */ #define UTMI_PLL_CTRL_REG 0x0 #define UTMI_PLL_CTRL_REFDIV_OFFSET 0 #define UTMI_PLL_CTRL_REFDIV_MASK (0x7f << UTMI_PLL_CTRL_REFDIV_OFFSET) @@ -53,7 +56,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 #define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK (0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET) -#define UTMI_TX_CH_CTRL_REG 0xC +/* UTMI Base registers */ +#define UTMI_TX_CH_CTRL_REG 0x0 #define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12 #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 @@ -61,7 +65,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define UTMI_TX_CH_CTRL_AMP_OFFSET 20 #define UTMI_TX_CH_CTRL_AMP_MASK (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET) -#define UTMI_RX_CH_CTRL0_REG 0x14 +#define UTMI_RX_CH_CTRL0_REG 0x8 #define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 #define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET) #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 @@ -69,19 +73,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK (0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET) -#define UTMI_RX_CH_CTRL1_REG 0x18 +#define UTMI_RX_CH_CTRL1_REG 0xC #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) -#define UTMI_CTRL_STATUS0_REG 0x24 +#define UTMI_CTRL_STATUS0_REG 0x18 #define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22 #define UTMI_CTRL_STATUS0_SUSPENDM_MASK (0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET) #define UTMI_CTRL_STATUS0_TEST_SEL_OFFSET 25 #define UTMI_CTRL_STATUS0_TEST_SEL_MASK (0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET) -#define UTMI_CHGDTC_CTRL_REG 0x38 +#define UTMI_CHGDTC_CTRL_REG 0x2C #define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8 #define UTMI_CHGDTC_CTRL_VDAT_MASK (0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET) #define UTMI_CHGDTC_CTRL_VSRC_OFFSET 10 diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c index 3ffd57e..91070c8 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c @@ -409,6 +409,7 @@ ArmadaSoCDescUtmiGet ( for (Index = 0; Index < MV_SOC_UTMI_PER_CP_COUNT; Index++) { Desc->UtmiPhyId = MV_SOC_UTMI_ID (UtmiIndex); Desc->UtmiBaseAddress = MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_BASE (Index); + Desc->UtmiPllAddress = MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_PLL_BASE; Desc->UtmiConfigAddress = MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_CFG_BASE; Desc->UsbConfigAddress = MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_USB_CFG_BASE; Desc++; diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c index 60ea06e..391b654 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c @@ -8,6 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "UtmiPhyLib.h" typedef struct { + EFI_PHYSICAL_ADDRESS UtmiPllAddr; EFI_PHYSICAL_ADDRESS UtmiBaseAddr; EFI_PHYSICAL_ADDRESS UsbCfgAddr; EFI_PHYSICAL_ADDRESS UtmiCfgAddr; @@ -95,6 +96,7 @@ STATIC VOID UtmiPhyConfig ( IN UINT32 UtmiIndex, + IN EFI_PHYSICAL_ADDRESS UtmiPllAddr, IN EFI_PHYSICAL_ADDRESS UtmiBaseAddr, IN EFI_PHYSICAL_ADDRESS UsbCfgAddr, IN EFI_PHYSICAL_ADDRESS UtmiCfgAddr, @@ -114,19 +116,19 @@ UtmiPhyConfig ( /* Select LPFR - 0x0 for 25Mhz/5=5Mhz */ Mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; Data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; - RegSet (UtmiBaseAddr + UTMI_PLL_CTRL_REG, Data, Mask); + RegSet (UtmiPllAddr + UTMI_PLL_CTRL_REG, Data, Mask); /* Impedance Calibration Threshold Setting */ Mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK; Data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET; - RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); + RegSet (UtmiPllAddr + UTMI_CALIB_CTRL_REG, Data, Mask); /* Start Impedance and PLL Calibration */ Mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK; Data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); Mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK; Data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); - RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); + RegSet (UtmiPllAddr + UTMI_CALIB_CTRL_REG, Data, Mask); /* Set LS TX driver strength coarse control */ Mask = UTMI_TX_CH_CTRL_AMP_MASK; @@ -168,6 +170,7 @@ STATIC UINTN UtmiPhyPowerUp ( IN UINT32 UtmiIndex, + IN EFI_PHYSICAL_ADDRESS UtmiPllAddr, IN EFI_PHYSICAL_ADDRESS UtmiBaseAddr, IN EFI_PHYSICAL_ADDRESS UsbCfgAddr, IN EFI_PHYSICAL_ADDRESS UtmiCfgAddr, @@ -192,7 +195,7 @@ UtmiPhyPowerUp ( /* Delay 10ms */ MicroSecondDelay (10000); - Data = MmioRead32 (UtmiBaseAddr + UTMI_CALIB_CTRL_REG); + Data = MmioRead32 (UtmiPllAddr + UTMI_CALIB_CTRL_REG); if ((Data & UTMI_CALIB_CTRL_IMPCAL_DONE_MASK) == 0) { DEBUG((DEBUG_ERROR, "UtmiPhy: Impedance calibration is not done\n")); Status = EFI_D_ERROR; @@ -201,7 +204,7 @@ UtmiPhyPowerUp ( DEBUG((DEBUG_ERROR, "UtmiPhy: PLL calibration is not done\n")); Status = EFI_D_ERROR; } - Data = MmioRead32 (UtmiBaseAddr + UTMI_PLL_CTRL_REG); + Data = MmioRead32 (UtmiPllAddr + UTMI_PLL_CTRL_REG); if ((Data & UTMI_PLL_CTRL_PLL_RDY_MASK) == 0) { DEBUG((DEBUG_ERROR, "UtmiPhy: PLL is not ready\n")); Status = EFI_D_ERROR; @@ -236,12 +239,14 @@ Cp110UtmiPhyInit ( MmioAnd32 (UtmiData->UsbCfgAddr, ~UTMI_USB_CFG_PLL_MASK); UtmiPhyConfig (UtmiData->PhyId, + UtmiData->UtmiPllAddr, UtmiData->UtmiBaseAddr, UtmiData->UsbCfgAddr, UtmiData->UtmiCfgAddr, UtmiData->UtmiPhyPort); Status = UtmiPhyPowerUp (UtmiData->PhyId, + UtmiData->UtmiPllAddr, UtmiData->UtmiBaseAddr, UtmiData->UsbCfgAddr, UtmiData->UtmiCfgAddr, @@ -292,6 +297,9 @@ UtmiPhyInit ( /* Get base address of UTMI phy */ UtmiData.UtmiBaseAddr = BoardDesc[Index].SoC->UtmiBaseAddress; + /* Get base address of PLL registers */ + UtmiData.UtmiPllAddr = BoardDesc[Index].SoC->UtmiPllAddress; + /* Get usb config address */ UtmiData.UsbCfgAddr = BoardDesc[Index].SoC->UsbConfigAddress; -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [edk2-platforms: PATCH 3/3] Marvell/Library: UtmiLib: Fix USB mux configuration 2020-05-12 18:59 [edk2-platforms: PATCH 0/3] Marvell UTMI fixes Marcin Wojtas 2020-05-12 18:59 ` [edk2-platforms: PATCH 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings Marcin Wojtas 2020-05-12 18:59 ` [edk2-platforms: PATCH 2/3] Marvell/Library: UtmiLib: fix pll initialization for the second port Marcin Wojtas @ 2020-05-12 18:59 ` Marcin Wojtas 2 siblings, 0 replies; 7+ messages in thread From: Marcin Wojtas @ 2020-05-12 18:59 UTC (permalink / raw) To: devel; +Cc: ard.biesheuvel, leif, mw, jsd, jaz, kostap If UTMI connected to USB Device, the MUX must be configured prior to the PHY init. Add missing register update in the relevant code. Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 1 + 1 file changed, 1 insertion(+) diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c index 391b654..5abbcb2 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c @@ -79,6 +79,7 @@ UtmiPhyPowerDown ( } else { Data = 0x0 << UTMI_USB_CFG_DEVICE_EN_OFFSET; } + RegSet (UsbCfgAddr, Data, Mask); /* Set Test suspendm mode */ Mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-05-13 14:27 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-05-12 18:59 [edk2-platforms: PATCH 0/3] Marvell UTMI fixes Marcin Wojtas 2020-05-12 18:59 ` [edk2-platforms: PATCH 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings Marcin Wojtas 2020-05-13 13:41 ` Leif Lindholm 2020-05-13 13:55 ` Marcin Wojtas 2020-05-13 14:27 ` Leif Lindholm 2020-05-12 18:59 ` [edk2-platforms: PATCH 2/3] Marvell/Library: UtmiLib: fix pll initialization for the second port Marcin Wojtas 2020-05-12 18:59 ` [edk2-platforms: PATCH 3/3] Marvell/Library: UtmiLib: Fix USB mux configuration Marcin Wojtas
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