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X-MS-Exchange-AntiSpam-MessageData: kQBkG30sm+S6RPJ4CNK3MXzsoOOm650CL88VNRfkfD1HH93TXb/2MyP9mL71Yiu1tmg7vZC7B5VmXFXHsWoB0w/M9X5LrNTwrmXpqgczOnSExSfftSy/OVBp6Ml3JSzF/TQxh6Yl2fGYiht999c9jIa5YRVc3oRlCBm+8DDyfXiHdin6+y7qjDNjwDzS4jg8LN14SpgnXgGtotn7hUlq3XwcQw+4ftQcDr+5h47xxi2EEEh80gaila6ShRnSa/Tk+VcbPBu0Hmm2nkQq7Oql1IhvuQkuPfbpq9TJ7UDv9c6FPWNVL3FgEulvIW017RJDyGuf94BKgxkzc1mP2uS4Yk4UJ9MO2Xra6SHHY6wSFplV9pzD5sL2o+rX4c6zVURJ8Hc4inuWt0n7pOKqUdYqIciPRrCkBg/W0NX1VPOR+4dM8KKcxvdhS88FeUvPZ/eSLkYbpMBVVgwW2CTbzmcXShOCTLLWZ+UmoK2csP4FzcuRTA7r7ilFAwJpFwKY/qee X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c37532b5-0650-430f-fdd6-08d7fddb26c5 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2020 23:03:18.8658 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qp2yhcdf91xVJn8cmGJgI8bK5lo4RfTaYE8r9B431sBJXmq4Dg64o8EhD4Q9gHLAvoOhU2GgqiGkdDSgt9n7Ew== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6381 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Wasim Khan PCIe layerscape controller supports CFG Shift feature. It can be enabled by setting BIT[28] of iATU Control 2 Register. Check PcdPciCfgShiftEnable to enable 'CFG Shift feature' in PCIe controller. if enable, PCIe layerscape controller shifts BDF from bits[27:12] to bits[31:16] and supports Enhanced Configuration Address Mapping (ECAM) mechanism. PCIe layerscape controller is ECAM complaint for bus[0x1-0xff]. So create outbound CFG windows from 1MB-256MB (255 buses) for type0/type1 configuration access. PCIe layerscape controller is Non-ECAM complaint for bus 0.It does not support device > 0 on bus 0. PciSegmentLib should handles this limitation. Signed-off-by: Vabhav Sharma Signed-off-by: Wasim Khan --- Silicon/NXP/NxpQoriqLs.dec | 3 ++ .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 3 ++ Silicon/NXP/Include/Pcie.h | 3 ++ .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 +++++++++++++++++-= ---- 4 files changed, 36 insertions(+), 8 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index bafdfd9f4298..293fd773fd3d 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -36,3 +36,6 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x00000502 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x00000503 gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x00000504 + +[PcdsDynamic.common] + gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600 diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Si= licon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf index 5ddb96e4fa6a..98cfb6aee6b0 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -38,3 +38,6 @@ [FixedPcd] gNxpQoriqLsTokenSpaceGuid.PcdNumPciController gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h index d5b5a3884e0a..ae85190180e8 100755 --- a/Silicon/NXP/Include/Pcie.h +++ b/Silicon/NXP/Include/Pcie.h @@ -63,6 +63,7 @@ #define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C #define IATU_VIEWPORT_OUTBOUND 0x0 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 +#define IATU_ENABLE_CFG_SHIFT_FEATURE BIT28 =20 // ATU Programming #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 @@ -82,4 +83,6 @@ #define SEG_IO_SIZE 0x10000 #define SEG_IO_BUS 0x0 =20 +#define CFG_SHIFT_ENABLE (PcdGetBool (PcdPciCfgShiftEnable)) + #endif diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index cf872370c7cd..f92863c60868 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -259,8 +259,17 @@ PcieOutboundSet ( MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0, (UINT32)Type); =20 - MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, - IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN); + if (CFG_SHIFT_ENABLE && + ((Type =3D=3D IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0) || + (Type =3D=3D IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1))) { + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, + (IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | + IATU_ENABLE_CFG_SHIFT_FEATURE) + ); + } else { + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN); + } } =20 /** @@ -291,12 +300,22 @@ PcieLsSetupAtu ( UINT64 Cfg0Size; UINT64 Cfg1Size; =20 - Cfg0BaseAddr =3D Cfg0Base; - Cfg1BaseAddr =3D Cfg1Base; - Cfg0BusAddress =3D SEG_CFG_BUS; - Cfg1BusAddress =3D SEG_CFG_BUS; - Cfg0Size =3D SEG_CFG_SIZE; - Cfg1Size =3D SEG_CFG_SIZE; + if (CFG_SHIFT_ENABLE) { + DEBUG ((DEBUG_INFO, "PCIe: CFG Shit Method Enabled \n")); + Cfg0BaseAddr =3D Cfg0Base + SIZE_1MB; + Cfg1BaseAddr =3D Cfg0Base + SIZE_2MB; + Cfg0BusAddress =3D SIZE_1MB; + Cfg1BusAddress =3D SIZE_2MB; + Cfg0Size =3D SIZE_1MB; + Cfg1Size =3D (SIZE_256MB - SIZE_1MB); // 255MB + } else { + Cfg0BaseAddr =3D Cfg0Base; + Cfg1BaseAddr =3D Cfg1Base; + Cfg0BusAddress =3D SEG_CFG_BUS; + Cfg1BusAddress =3D SEG_CFG_BUS; + Cfg0Size =3D SEG_CFG_SIZE; + Cfg1Size =3D SEG_CFG_SIZE; + } =20 // iATU : OUTBOUND WINDOW 1 : CFG0 PcieOutboundSet (Pcie, --=20 2.7.4