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dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=oss.nxp.com; Received: from VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) by VE1PR04MB6381.eurprd04.prod.outlook.com (2603:10a6:803:119::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.27; Thu, 21 May 2020 23:03:25 +0000 Received: from VE1PR04MB6702.eurprd04.prod.outlook.com ([fe80::81c4:97a6:7592:f225]) by VE1PR04MB6702.eurprd04.prod.outlook.com ([fe80::81c4:97a6:7592:f225%7]) with mapi id 15.20.3021.020; Thu, 21 May 2020 23:03:25 +0000 From: Wasim Khan To: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, vabhav.sharma@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, leif@nuviainc.com, jon@solid-run.com CC: Wasim Khan Subject: [PATCH edk2-platforms 06/16] Silicon/NXP: PciHostBridgeLib: add Workaround for A-011451 Date: Fri, 22 May 2020 04:32:09 +0530 Message-ID: <1590102139-16588-7-git-send-email-wasim.khan@oss.nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590102139-16588-1-git-send-email-wasim.khan@oss.nxp.com> References: <1590102139-16588-1-git-send-email-wasim.khan@oss.nxp.com> X-ClientProxiedBy: PN1PR01CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::11) To VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) Return-Path: wasim.khan@oss.nxp.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wasimk-VirtualBox.nxp.com (157.47.200.219) by PN1PR01CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3021.23 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 5Khb0dMbdni3vr7yMDC0b00CfVC/gz16LnRKutIxZjJMiPCYNCzkxqQBy0T5crKlUxVHhyLRPY4h5T8pbYmkkT4W8o1GRN7mJaF2Umue/Pq+fycyyspNMeC13QtG2Jtd9P+u9Dwwog+RB+Q2oZ8y21cHEHOz60qo95sRkOHULfUcqK0l+SOQmAI/Ja2c1F9tYeK8ZPiFWYRHU4WvPbbRCs5BP/5yHD4nvKKoVAUk0y6eu8ODsRIPs3pkytVfef9U2poNCPy9Su9vyzXl5+l9nCvHGb3M3i0eQmV9t6MK0fUoNfUP8DS8LN+biz1skJ0HDmqWGHOBzAY7vw79ripEYRz4c5/zdjITiPrwyaM9Oge1fFCQ6woJxqvLLC2UKiQTrZXu93Ziwt2noOlVYPCtaVQmU6Ykhtvm73GBXU7/ULC0j+bDnDCyTKrxm/16CXq6OuLHK2h0YCkdmuLEg+6zj9Qeh+Czo7mqMLpB4u7UXjySI4NGr8GMCOFB7Usojndy X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d677a868-f3a1-4690-5a02-08d7fddb2a4a X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2020 23:03:24.8483 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hwFio0k9RmG27r0c00l7zmEHYjpwc1/NT+R1SV9BIO96BTUl2KrGViM7l2ZLiSk2Bg/uIuiqiKbHzI6F3dlqGw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6381 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Wasim Khan When PCIe Layerscape Gen4 controller is sending multiple split completions and ACK latency expires indicating that ACK should be send at priority. But because of large number of split completions and FC update DLLP,the controller does not give priority to ACK transmission. This results into ACK latency timer timeout error at the link partner and the pending TLPs are replayed by the link partner again. Workaround: Reduce the ACK latency timeout value. Signed-off-by: Vabhav Sharma Signed-off-by: Wasim Khan --- Silicon/NXP/Include/Pcie.h | 4 ++++ Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h index 4c41c3585a8b..bc35570f79bc 100755 --- a/Silicon/NXP/Include/Pcie.h +++ b/Silicon/NXP/Include/Pcie.h @@ -205,4 +205,8 @@ STATIC inline VOID PciLsGen4Write32 ( MmioWrite32 (Dbi + OFFSET_TO_PAGE_ADDR (Offset), Value); } } + +#define GPEX_ACK_REPLAY_TO 0x438 +#define ACK_LAT_TO_VAL_SHIFT 0 +#define ACK_LAT_TO_VAL_MASK 0x1fff #endif diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index d9944313da21..bacdc29d60d6 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -556,6 +556,12 @@ PcieSetupCntrl ( if (PCI_LS_GEN4_CTRL) { // PCIe LsGen4 Controller Setup =20 + // Workaround for A-011451 + Val =3D PciLsGen4Read32 ((UINTN)Pcie, GPEX_ACK_REPLAY_TO); + Val &=3D ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT); + Val |=3D (4 << ACK_LAT_TO_VAL_SHIFT); + PciLsGen4Write32 ((UINTN)Pcie, GPEX_ACK_REPLAY_TO, Val); + //Fix Class Code Val =3D PciLsGen4Read32 ((UINTN)Pcie, GPEX_CLASSCODE); Val &=3D ~(GPEX_CLASSCODE_MASK << GPEX_CLASSCODE_SHIFT); --=20 2.7.4