[PATCH edk2-platforms 07/16] Silicon/NXP: PciHostBridgeLib: Dump Layerscale Gen4 ATU windows

[Wasim Khan <wasim.khan@oss.nxp.com>]

From: Wasim Khan <wasim.khan@nxp.com>

Dump ATU windows for PCIe LsGen4 controller if PcdPciDebug
is enabled.

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
 .../Library/PciHostBridgeLib/PciHostBridgeLib.inf  |  1 +
 .../Library/PciHostBridgeLib/PciHostBridgeLib.c    | 34 ++++++++++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index b777acdc103f..df1590172e15 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -38,6 +38,7 @@ [FixedPcd]
   gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
   gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
   gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
+  gNxpQoriqLsTokenSpaceGuid.PcdPciDebug
 
 [Pcd]
   gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
index bacdc29d60d6..1de20c621dc0 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -413,6 +413,36 @@ PcieLsSetupAtu (
 }
 
 /**
+  Dump PCIe LsGen4 ATU
+
+  @param Pcie     Address of PCIe host controller.
+**/
+VOID LsGen4DumpAtu (
+  IN EFI_PHYSICAL_ADDRESS Pcie
+  )
+{
+  UINT32 Cnt;
+  for (Cnt = 0; Cnt <= IATU_REGION_INDEX6; Cnt++) {
+    DEBUG ((DEBUG_INFO,"APIO WINDOW%d:\n", Cnt));
+    DEBUG ((DEBUG_INFO,"\tLOWER PHYS 0x%08x\n",
+            PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_AXI_WIN (Cnt))));
+    DEBUG ((DEBUG_INFO,"\tUPPER PHYS 0x%08x\n",
+            PciLsGen4Read32 ((UINTN)Pcie, PAB_EXT_AXI_AMAP_AXI_WIN (Cnt))));
+    DEBUG ((DEBUG_INFO,"\tLOWER BUS  0x%08x\n",
+            PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_PEX_WIN_L (Cnt))));
+    DEBUG ((DEBUG_INFO,"\tUPPER BUS  0x%08x\n",
+            PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_PEX_WIN_H (Cnt))));
+    DEBUG ((DEBUG_INFO,"\tSIZE      0x%08x\n",
+            PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_CTRL (Cnt)) &
+            (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT)));
+    DEBUG ((DEBUG_INFO,"\tEXT_SIZE        0x%08x\n",
+            PciLsGen4Read32 ((UINTN)Pcie, PAB_EXT_AXI_AMAP_SIZE (Cnt))));
+    DEBUG ((DEBUG_INFO,"\tCTRL:        0x%08x\n",
+            PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_CTRL (Cnt))));
+  }
+}
+
+/**
   Function to set-up ATU windows for PCIe LayerscapeGen4 controller
 
   @param Pcie      Address of PCIe host controller
@@ -484,6 +514,10 @@ PcieLsGen4SetupAtu (
                             Mem64Base,
                             Mem64Base,
                             SIZE_4GB);
+
+  if (FixedPcdGetBool (PcdPciDebug) == TRUE) {
+    LsGen4DumpAtu (Pcie);
+  }
 }
 
 /**
-- 
2.7.4