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X-MS-Exchange-AntiSpam-MessageData: /L8tF1VYDrhAlUKaarBl4gyjj/idGxawcm/K2fF5kuwJD/tGRIKGLDs7CZWkxLV6XbA0uaGV38C3znZG3cuW9fwSI2EU9smFa/1iblM6d6WBi/JT4nFsC7EZIXyrK9hyaMmLGeFGt6sDoNYiGNHyRGK2A53oQyyK8M9qjj7tcpMYuusUHaQSY+7sbex2qGE5qUoQ4VxNu/y3pKz2hwfO11mcycuDlcaoAWUAojHzphkdp8w0fsZi0fWxUeOiPkObjAYJ2y10SpQbRcDpYhGGvX0TxIoQ+HZRg7fVWKEICsU7rBfFw3x5YM52vsc9Xj1jQ9lBWWVSSMV5a1ZIozfFDp54u5KFbwxkEU4PdFRnmT6V2T1risRGypAW0oOwwf23bj80HQMSfsBEEQzywDHmqMzoVm43v+YQ8CXMC0QzCaWc6XArFdzBRYZVnlF7rpiM1vilj7SSC99PSmDb8ZHEEPZTjjMjyGXIA+F5dtPFv7M= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c3c362ca-4ab9-4bdf-fbea-08d7fddb2dc9 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2020 23:03:30.8279 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 02zrm6I7uLTA2Lc12E+mC4K6nQZqdqE7xx7DMW5kraCmIcGo2ZsrseKWJZECA4+xeQYdHNRvQMExdrmwxBl5IA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6381 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Wasim Khan Dump ATU windows for PCIe Layerscape controller if PcdPciDebug is enabled. Signed-off-by: Wasim Khan --- .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 42 ++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index 1de20c621dc0..3ad526218bcf 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -297,6 +297,44 @@ PcieOutboundSet ( } =20 /** + Dump PCIe Layerscape ATU + + @param Pcie Address of PCIe host controller. +**/ +VOID LsDumpAtu ( + IN EFI_PHYSICAL_ADDRESS Pcie + ) +{ + UINT32 Cnt; + for (Cnt =3D 0; Cnt <=3D IATU_REGION_INDEX7; Cnt++) { + MmioWrite32 ((UINTN)Pcie + IATU_VIEWPORT_OFF, + (UINT32)(IATU_VIEWPORT_OUTBOUND | Cnt)); + + DEBUG ((DEBUG_INFO, "iATU%d:\n",Cnt)); + DEBUG ((DEBUG_INFO, "\tLOWER PHYS 0x%08x\n", + MmioRead32 ((UINTN)Pcie + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0)))= ; + + DEBUG ((DEBUG_INFO, "\tUPPER PHYS 0x%08x\n", + MmioRead32 ((UINTN)Pcie + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0)= )); + + DEBUG ((DEBUG_INFO, "\tLOWER BUS 0x%08x\n", + MmioRead32 ((UINTN)Pcie + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0)= )); + + DEBUG ((DEBUG_INFO, "\tUPPER BUS 0x%08x\n", + MmioRead32 ((UINTN)Pcie + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_= 0))); + + DEBUG ((DEBUG_INFO, "\tLIMIT 0x%08x\n", + MmioRead32 ((UINTN)Pcie + IATU_LIMIT_ADDR_OFF_OUTBOUND_0))); + + DEBUG ((DEBUG_INFO, "\tCR1 0x%08x\n", + MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_1_OFF_OUTBOUND_0)))= ; + + DEBUG ((DEBUG_INFO, "\tCR2 0x%08x\n", + MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_2_OFF_OUTBOUND_0)))= ; + } +} + +/** Function to set-up iATU windows for Layerscape PCIe controller =20 @param Pcie Address of PCIe host controller @@ -410,6 +448,10 @@ PcieLsSetupAtu ( SEG_IO_BUS, SEG_IO_SIZE ); + + if (FixedPcdGetBool (PcdPciDebug) =3D=3D TRUE) { + LsDumpAtu (Pcie); + } } =20 /** --=20 2.7.4