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dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=oss.nxp.com; Received: from VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) by VE1PR04MB6367.eurprd04.prod.outlook.com (2603:10a6:803:11a::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.27; Tue, 26 May 2020 08:38:48 +0000 Received: from VE1PR04MB6702.eurprd04.prod.outlook.com ([fe80::81c4:97a6:7592:f225]) by VE1PR04MB6702.eurprd04.prod.outlook.com ([fe80::81c4:97a6:7592:f225%7]) with mapi id 15.20.3021.029; Tue, 26 May 2020 08:38:48 +0000 From: Wasim Khan To: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, vabhav.sharma@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, leif@nuviainc.com, jon@solid-run.com CC: Wasim Khan Subject: [PATCH edk2-platforms v2 09/16] Silicon/NXP: Implement PciSegmentLib for PCIe Layerscape Controller Date: Tue, 26 May 2020 14:07:14 +0530 Message-ID: <1590482241-13132-10-git-send-email-wasim.khan@oss.nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590482241-13132-1-git-send-email-wasim.khan@oss.nxp.com> References: <1590482241-13132-1-git-send-email-wasim.khan@oss.nxp.com> X-ClientProxiedBy: BM1PR0101CA0015.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:18::25) To VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) Return-Path: wasim.khan@oss.nxp.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wasimk-VirtualBox.nxp.com (171.79.147.152) by BM1PR0101CA0015.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:18::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3021.23 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 03yt3ti8qXaVgKBC0dLdeI3MZFZNQuP90ADYUxeGzHW2n98GmGVKMaUeK/G3hRyWXtZP+Gt5grzdLA2c/j3qiHGKMlLoVK06CrAt+He+rokdOHMhMmYTwxPTdrjaTr4E2jw2uUT+H5EXSiLDnxMGai7HmkRzCfCLumv+ZGZyGUIRECfPHEeJ987kpf5vHkwvMok5vCLFC1n+RCPlU/3+2t6eIju6UbgMQ6uzB06Oczmw8vEzj+zlWL6IdErPaooW1BRdK4Dci+CacYFjD+5x6VN2nBo1x5LhNBJ5GgM2NLUTI3tbKBzW/bJ6rhGgRbiRnSuNeZcqyScHYyJ4vOdg7xmAkry45HZYr6pNPMPqXsxA83v54caW3cvfhRYqHkMoReRrJbzrX5mBuba2paN7G6+99jgcwvSUwTiLmRQnJU2W3uiCzMBGOKnmiSn3hSrACEoocI2vPjpnoJAUU2o/EHaDmUYdj2jvYVuIX54HSi0= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 21a3756b-e93c-47b8-218a-08d801503256 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2020 08:38:48.4678 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: M1YYyMQeYEYYOTcprr4tTCgPn48WM7EZj8EVA3eDOpwXQ7ILav5e4BJj1WvVMWRRo3iriMdBsCMT15PIH3sFag== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6367 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Wasim Khan We have different PCI config space region for bus 0 (Controller space) and bus[0x1-0xff] on NXP SoCs with PCIe LS controller. Add PciSegmentLib for PCIe LS controller. For config transactions for Bus0: - Config transaction address =3D PCIe controller address + offset For config transactions for Bus[0x1-0xff]: - PCIe IP requires target BDF to be written at bit[31:16] of PCIe type0/type1 outbound window. - Config transaction address =3D PCIe config space address + offset Co-authored-by: Vabhav Sharma Co-authored-by: Wasim Khan Signed-off-by: Wasim Khan --- Notes: V2: - Removed Signed-off and added Co-authored-by for co-author - Incorporated review comments: - Remove outer () while calculating Target - Use (Bus > 0) instead of (Bus) Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf | 32 + Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 612 ++++++++++++++++= ++++ 2 files changed, 644 insertions(+) diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/= NXP/Library/PciSegmentLib/PciSegmentLib.inf new file mode 100755 index 000000000000..a36e79239b33 --- /dev/null +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf @@ -0,0 +1,32 @@ +## @file +# PCI Segment Library for NXP SoCs with multiple RCs +# +# Copyright 2018-2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PciSegmentLib + FILE_GUID =3D c9f59261-5a60-4a4c-82f6-1f520442e100 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciSegmentLib|DXE_DRIVER + CONSTRUCTOR =3D PciSegLibInit + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + PcdLib + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/NX= P/Library/PciSegmentLib/PciSegmentLib.c new file mode 100755 index 000000000000..d0bacca3d0d7 --- /dev/null +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c @@ -0,0 +1,612 @@ +/** @file + PCI Segment Library for NXP SoCs with multiple RCs + + Copyright 2018-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + PciCfgWidthUint8 =3D 0, + PciCfgWidthUint16, + PciCfgWidthUint32, + PciCfgWidthMax +} PCI_CFG_WIDTH; + +/** + Assert the validity of a PCI Segment address. + A valid PCI Segment address should not contain 1's in bits 28..31 and 48= ..63 + + @param A The address to validate. + @param M Additional bits to assert to be zero. + +**/ +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) =3D=3D 0) + +STATIC +UINT64 +PciLsCfgTarget ( + IN EFI_PHYSICAL_ADDRESS Dbi, + IN UINT64 Address, + IN UINT16 Segment, + IN UINT8 Bus, + IN UINT16 Offset + ) +{ + UINT32 Target; + + Target =3D (((Address >> 20) & 0xFF) << 24) | + (((Address >> 15) & 0x1F) << 19) | + (((Address >> 12) & 0x7) << 16); + + if (Bus > 1) { + MmioWrite32 ((UINTN)Dbi + IATU_VIEWPORT_OFF, IATU_VIEWPORT_OUTBOUND | = IATU_REGION_INDEX1); + } else { + MmioWrite32 ((UINTN)Dbi + IATU_VIEWPORT_OFF, IATU_VIEWPORT_OUTBOUND | = IATU_REGION_INDEX0); + } + + MmioWrite32 ((UINTN)Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0, Target); + + if (Bus > 1) { + return PCI_SEG0_MMIO_MEMBASE + PCI_BASE_DIFF * Segment + SEG_CFG_SIZE = + Offset; + } else { + return PCI_SEG0_MMIO_MEMBASE + PCI_BASE_DIFF * Segment + Offset; + } +} + +/** + Function to return PCIe Physical Address(PCIe view) or Controller + Address(CPU view) for different RCs + + @param Address Address passed from bus layer. + @param Segment Segment number for Root Complex. + @param Offset Config space register offset. + @param Bus PCIe Bus number. + + @return Return PCIe CPU or Controller address. + +**/ +STATIC +UINT64 +PciLsGetConfigBase ( + IN UINT64 Address, + IN UINT16 Segment, + IN UINT16 Offset, + IN UINT8 Bus + ) +{ + UINT32 CfgAddr; + + CfgAddr =3D (UINT16)Offset; + if (Bus > 0) { + return PciLsCfgTarget (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment= , Address, Segment, Bus, Offset); + } else { + return PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF * Segment + CfgAddr; + } +} + +/** + Function to return PCIe Physical Address(PCIe view) or Controller + Address(CPU view) for different RCs + + @param Address Address passed from bus layer. + @param Segment Segment number for Root Complex. + @param Offset Config space register offset. + + @return Return PCIe CPU or Controller address. + +**/ +STATIC +UINT64 +PciSegmentLibGetConfigBase ( + IN UINT64 Address, + IN UINT16 Segment, + IN UINT16 Offset + ) +{ + UINT8 Bus; + + Bus =3D ((UINT32)Address >> 20) & 0xff; + return PciLsGetConfigBase (Address, Segment, Offset, Bus); +} + +/** + Internal worker function to read a PCI configuration register. + + @param Address The address that encodes the Segment, PCI Bus, Device, + Function and Register. + @param Width The width of data to read + + @return The value read from the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibReadWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width + ) +{ + UINT64 Base; + UINT16 Offset; + UINT16 Segment; + + Segment =3D (Address >> 32); + Offset =3D (Address & 0xfff ); + + Base =3D PciSegmentLibGetConfigBase (Address, Segment, Offset); + + // ignore devices > 0 on bus 0 + if ((Address & 0xff00000) =3D=3D 0 && (Address & 0xf8000) !=3D 0) { + return MAX_UINT32; + } + + // ignore device > 0 on bus 1 + if ((Address & 0xfe00000) =3D=3D 0 && (Address & 0xf8000) !=3D 0) { + return MAX_UINT32; + } + + switch (Width) { + case PciCfgWidthUint8: + return MmioRead8 (Base); + case PciCfgWidthUint16: + return MmioRead16 (Base); + case PciCfgWidthUint32: + return MmioRead32 (Base); + default: + ASSERT (FALSE); + } + + return CHAR_NULL; +} + +/** + Internal worker function to writes a PCI configuration register. + + @param Address The address that encodes the Segment, PCI Bus, Device, + Function and Register. + @param Width The width of data to write + @param Data The value to write. + + @return The value written to the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibWriteWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width, + IN UINT32 Data + ) +{ + UINT64 Base; + UINT32 Offset; + UINT16 Segment; + + Segment =3D (Address >> 32); + Offset =3D (Address & 0xfff ); + + Base =3D PciSegmentLibGetConfigBase (Address, Segment, Offset); + + // ignore devices > 0 on bus 0 + if ((Address & 0xff00000) =3D=3D 0 && (Address & 0xf8000) !=3D 0) { + return Data; + } + + // ignore device > 0 on bus 1 + if ((Address & 0xfe00000) =3D=3D 0 && (Address & 0xf8000) !=3D 0) { + return MAX_UINT32; + } + + switch (Width) { + case PciCfgWidthUint8: + MmioWrite8 (Base , Data); + break; + case PciCfgWidthUint16: + MmioWrite16 (Base , Data); + break; + case PciCfgWidthUint32: + MmioWrite32 (Base , Data); + break; + default: + ASSERT (FALSE); + } + + return Data; +} + +/** + Register a PCI device so PCI configuration registers may be accessed aft= er + SetVirtualAddressMap(). + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Bus, D= evice, + Function and Register. + + @retval RETURN_SUCCESS The PCI device was registered for runti= me access. + @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PC= I device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciSegmentRegisterForRuntimeAccess ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + return RETURN_UNSUPPORTED; +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Addr= ess. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, + and Register. + + @return The 8-bit PCI configuration register specified by Address. + +**/ +UINT8 +EFIAPI +PciSegmentRead8 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8); +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with th= e value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentWrite8 ( + IN UINT64 Address, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Valu= e); +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Add= ress. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + + @return The 16-bit PCI configuration register specified by Address. + +**/ +UINT16 +EFIAPI +PciSegmentRead16 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16); +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with t= he + value specified by Value. + + Value is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT16 +EFIAPI +PciSegmentWrite16 ( + IN UINT64 Address, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Va= lue); +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Add= ress. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, + and Register. + + @return The 32-bit PCI configuration register specified by Address. + +**/ +UINT32 +EFIAPI +PciSegmentRead32 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with t= he + value specified by Value. + + Value is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, + Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT32 +EFIAPI +PciSegmentWrite32 ( + IN UINT64 Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value); +} + +/** + Reads a range of PCI configuration registers into a caller supplied buff= er. + + Reads the range of PCI configuration registers specified by StartAddress= and + Size into the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be read. Size is + returned. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment,= Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +PciSegmentReadBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D SIZE_4KB); + + if (Size =3D=3D 0) { + return Size; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // + // Read a byte if StartAddress is byte aligned + // + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) { + // + // Read a word if StartAddress is word aligned + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + BIT0; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Read as many double words as possible + // + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Read the last remaining word if exist + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Read the last remaining byte if exist + // + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + } + + return ReturnValue; +} + + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddres= s and + Size from the buffer specified by Buffer. This function only allows the = PCI + configuration registers from a single PCI function to be written. Size i= s + returned. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment,= Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer containing the data to wri= te. + + @return The parameter of Size. + +**/ +UINTN +EFIAPI +PciSegmentWriteBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D SIZE_4KB); + + if (Size =3D=3D 0) { + return Size; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // + // Write a byte if StartAddress is byte aligned + // + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) { + // + // Write a word if StartAddress is word aligned + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + BIT0; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Write as many double words as possible + // + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Write the last remaining word if exist + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + BIT0; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Write the last remaining byte if exist + // + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); + } + + return ReturnValue; +} + +EFI_STATUS +PciSegLibInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} --=20 2.7.4