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charset=UTF-8 Content-Transfer-Encoding: quoted-printable From: Wasim Khan With PCIe LsGen4 controller, clearing the Bus Master Enable bit in Command register blocks all outbound transactions to be sent out in RC mode. According to PCI Express base specification, the Command register=E2=80=99s Bus Master Enable bit of a PCI Express RC controller can only control the forwarding of memory requests received at its root port in the upstream direction. In other words, clearing the Bus Master Enable bit must not block all outbound transactions to be sent out toward RC=E2=80=99s downstream devices. Due to this erratum, when the Command register=E2=80=99s Bus Master Enable bit is cleared, all the outbou= nd transactions from the device=E2=80=99s internal bus masters, including but not limited to configuration read and write transactions, are terminated with the slave error (SLVERR) response status on the PCI Express RC controller=E2=80=99s internal AXI bus interface. Signed-off-by: Wasim Khan --- Notes: V2: - Addressed review comments to: - Drop outer () while calculating Target - Use (Bus > 0) instead of (Bus) Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/NX= P/Library/PciSegmentLib/PciSegmentLib.c index 09ce620ef988..572fbb195c19 100755 --- a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c @@ -39,6 +39,21 @@ static BOOLEAN PciLsGen4Ctrl; =20 STATIC VOID +PciLsGen4SetBusMaster ( + IN EFI_PHYSICAL_ADDRESS Dbi + ) +{ + UINT32 Val; + + //Make sure the Master Enable bit not cleared + Val =3D PciLsGen4Read32 ((UINTN)Dbi, PCI_COMMAND_OFFSET); + if (!(Val & EFI_PCI_COMMAND_BUS_MASTER)) { + PciLsGen4Write32 ((UINTN)Dbi, PCI_COMMAND_OFFSET, Val | EFI_PCI_COMMAN= D_BUS_MASTER); + } +} + +STATIC +VOID PcieCfgSetTarget ( IN EFI_PHYSICAL_ADDRESS Dbi, IN UINT32 Target) @@ -71,6 +86,8 @@ PciLsGen4GetConfigBase ( UINT32 Target; =20 if (Bus > 0) { + PciLsGen4SetBusMaster (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF* Segment)= ; + Target =3D (((Address >> 20) & 0xFF) << 24) | (((Address >> 15) & 0x1F) << 19) | (((Address >> 12) & 0x7) << 16); --=20 2.7.4