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dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=oss.nxp.com; Received: from VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) by VE1PR04MB6367.eurprd04.prod.outlook.com (2603:10a6:803:11a::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3021.27; Tue, 26 May 2020 08:38:26 +0000 Received: from VE1PR04MB6702.eurprd04.prod.outlook.com ([fe80::81c4:97a6:7592:f225]) by VE1PR04MB6702.eurprd04.prod.outlook.com ([fe80::81c4:97a6:7592:f225%7]) with mapi id 15.20.3021.029; Tue, 26 May 2020 08:38:26 +0000 From: Wasim Khan To: devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, vabhav.sharma@nxp.com, V.Sethi@nxp.com, ard.biesheuvel@arm.com, leif@nuviainc.com, jon@solid-run.com CC: Wasim Khan Subject: [PATCH edk2-platforms v2 05/16] Silicon/NXP: PciHostBridgeLib: Setup PCIe LsGen4 Controller and ATU Windows Date: Tue, 26 May 2020 14:07:10 +0530 Message-ID: <1590482241-13132-6-git-send-email-wasim.khan@oss.nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590482241-13132-1-git-send-email-wasim.khan@oss.nxp.com> References: <1590482241-13132-1-git-send-email-wasim.khan@oss.nxp.com> X-ClientProxiedBy: BM1PR0101CA0015.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:18::25) To VE1PR04MB6702.eurprd04.prod.outlook.com (2603:10a6:803:123::13) Return-Path: wasim.khan@oss.nxp.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wasimk-VirtualBox.nxp.com (171.79.147.152) by BM1PR0101CA0015.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:18::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3021.23 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 3DajCFIORDIaNgvs5LiDoQ+GzTyEPfMSpme2S+rwmxLdNFn9dwVFRJuIv20S06QKpu+FaNHN52AgY6lZP8RwoeyIbJ9O64byZ/EeZVjG6cy6TRNg1U8X1yq495MTf0O2rhk2QEMHywgwIvqX4jpjFji2dxsNxo5H7hfW+xhQGSegbZez71ZH3xnOCLIP8+hCaSzfSnIMLeVZFcbNM/fXgGmnB7yepVv8JEzWxNNcmBmPsklJ7z/dVjOuIsYJ5kqh7eYCRBlvpJu2swUjCNJwvIRw5JIO28VgVQCKkGkPTyyn2N2w+c/TLhd+gXqGUBFjFXMxoAM4utMPDHgvvRwLk0Ipl072lM5Ixx+83T7sC0TspaUIQzz/ztLYBiXENzR/6XCHz6B4+ahjegSgYv6LPlVoe4flMXUcJWT97O7QGXMYn7xXRwe7c4lENi+C9D9FTldAiBPcfRYIvWHS98ToeO/FwDugGTxmLq+9O1JpsjA= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 06b167e8-54f7-4731-6340-08d8015025b0 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2020 08:38:26.2475 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: EVxpGd0/KGuXRQ91Nk28diGj4c1H/Cz9CgAO7OY9p7aH/zkfQtZtcMtXceHW5vEGnvtbDl3TB0hW5E5YLI46SQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6367 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Wasim Khan Setup PCIe LayerscapeGen4 controller and setup CFG, IO, MMIO and MMIO64 iATU windows. Check for PcdPciLsGen4Ctrl to enable LsGen4 PCIe controller. Co-authored-by: Vabhav Sharma Co-authored-by: Wasim Khan Signed-off-by: Wasim Khan --- Notes: V2: - Removed Signed-off and added Co-authored-by for co-author - Added logic to create MMIO64 ATU windows as per MMIO64 available spac= e Silicon/NXP/NxpQoriqLs.dec | 1 + Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 + Silicon/NXP/Include/Pcie.h | 120 ++++++++++ Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 247 ++++++++++= ++++++---- 4 files changed, 328 insertions(+), 41 deletions(-) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index 5358aaeb037e..d4d3057af509 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -38,3 +38,4 @@ [PcdsFixedAtBuild.common] =20 [PcdsDynamic.common] gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600 + gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl|FALSE|BOOLEAN|0x00000601 diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Si= licon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf index 99807d5beb1f..aa5a9dec7c34 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -40,3 +40,4 @@ [FixedPcd] =20 [Pcd] gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable + gNxpQoriqLsTokenSpaceGuid.PcdPciLsGen4Ctrl diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h index f7c18c3aa094..b7d46f3a3bd2 100755 --- a/Silicon/NXP/Include/Pcie.h +++ b/Silicon/NXP/Include/Pcie.h @@ -81,5 +81,125 @@ #define SEG_IO_BUS 0x0 =20 #define CFG_SHIFT_ENABLE (PcdGetBool (PcdPciCfgShiftEnable)) +#define PCI_LS_GEN4_CTRL (PcdGetBool (PcdPciLsGen4Ctrl)) =20 +// PCIe Layerscape Gen4 Controller +#define GPEX_CLASSCODE 0x474 +#define GPEX_CLASSCODE_SHIFT 16 +#define GPEX_CLASSCODE_MASK 0xffff +#define PAB_AXI_PIO_CTRL(Idx) (0x840 + 0x10 * Idx) +#define APIO_EN 0x1 +#define MEM_WIN_EN 0x1 << 1 +#define IO_WIN_EN 0x1 << 2 +#define CFG_WIN_EN 0x1 << 3 +#define PAB_PEX_PIO_CTRL(Idx) (0x8c0 + 0x10 * Idx) +#define PPIO_EN (0x1 << 0) +#define PAB_PEX_PIO_STAT(Idx) (0x8c4 + 0x10 * Idx) +#define PAB_PEX_PIO_MT_STAT(Idx) (0x8c8 + 0x10 * Idx) +#define PEX_AMAP_CTRL_TYPE_SHIFT 0x1 +#define PEX_AMAP_CTRL_EN_SHIFT 0x0 +#define PEX_AMAP_CTRL_TYPE_MASK 0x3 +#define PEX_AMAP_CTRL_EN_MASK 0x1 +#define PAB_PEX_AMAP_CTRL(Idx) (0x4ba0 + 0x10 * Idx) +#define PAB_EXT_PEX_AMAP_SIZE(Idx) (0xbef0 + 0x04 * Idx) +#define PAB_PEX_AMAP_AXI_WIN(Idx) (0x4ba4 + 0x10 * Idx) +#define PAB_EXT_PEX_AMAP_AXI_WIN(Idx) (0xb4a0 + 0x04 * Idx) +#define PAB_PEX_AMAP_PEX_WIN_L(Idx) (0x4ba8 + 0x10 * Idx) +#define PAB_PEX_AMAP_PEX_WIN_H(Idx) (0x4bac + 0x10 * Idx) +#define PAB_CTRL 0x808 +#define PAB_CTRL_APIO_EN 0x1 +#define PAB_CTRL_PPIO_EN (0x1 << 1) +#define PAB_CTRL_PAGE_SEL_SHIFT 13 +#define PAB_CTRL_PAGE_SEL_MASK 0x3f +#define INDIRECT_ADDR_BNDRY 0xc00 +#define PAGE_IDX_SHIFT 10 +#define PAGE_ADDR_MASK 0x3ff +#define PAB_AXI_AMAP_CTRL(Idx) (0xba0 + 0x10 * Idx) +#define PAB_EXT_AXI_AMAP_SIZE(Idx) (0xbaf0 + 0x4 * Idx) +#define PAB_AXI_AMAP_AXI_WIN(Idx) (0xba4 + 0x10 * Idx) +#define PAB_EXT_AXI_AMAP_AXI_WIN(Idx) (0x80a0 + 0x4 * Idx) +#define PAB_AXI_AMAP_PEX_WIN_L(Idx) (0xba8 + 0x10 * Idx) +#define PAB_AXI_AMAP_PEX_WIN_H(Idx) (0xbac + 0x10 * Idx) +#define PAB_AXI_TYPE_CFG 0x00 +#define PAB_AXI_TYPE_IO 0x01 +#define PAB_AXI_TYPE_MEM 0x02 +#define AXI_AMAP_CTRL_EN 0x1 +#define AXI_AMAP_CTRL_TYPE_SHIFT 1 +#define AXI_AMAP_CTRL_TYPE_MASK 0x3 +#define AXI_AMAP_CTRL_SIZE_SHIFT 10 +#define AXI_AMAP_CTRL_SIZE_MASK 0x3fffff + + +#define OFFSET_TO_PAGE_IDX(Off) ((Off >> PAGE_IDX_SHIFT) \ + & PAB_CTRL_PAGE_SEL_MASK) + +#define OFFSET_TO_PAGE_ADDR(Off) ((Off & PAGE_ADDR_MASK) \ + | INDIRECT_ADDR_BNDRY) +/** + Function to set page for LsGen4 Ctrl + + @param Dbi GPEX host controller address. + @param PgIdx The page index to select + +**/ +STATIC inline VOID PciLsGen4SetPg ( + IN EFI_PHYSICAL_ADDRESS Dbi, + IN UINT8 PgIdx + ) +{ + UINT32 Val; + Val =3D MmioRead32 (Dbi + PAB_CTRL); + Val &=3D ~(PAB_CTRL_PAGE_SEL_MASK << PAB_CTRL_PAGE_SEL_SHIFT); + Val |=3D (PgIdx & PAB_CTRL_PAGE_SEL_MASK) << PAB_CTRL_PAGE_SEL_SHIFT; + MmioWrite32 (Dbi + PAB_CTRL, Val); +} + +/** + Function to read LsGen4 PCIe controller config space + LsGen4 PCIe controller requires page number to be set + in Bridge Control Register(PAB) for offset > 3KB. + + @param Dbi GPEX host controller address. + @param Offset Offset to read from + +**/ +STATIC inline INTN PciLsGen4Read32 ( + IN EFI_PHYSICAL_ADDRESS Dbi, + IN UINT32 Offset + ) +{ + if (Offset < INDIRECT_ADDR_BNDRY) { + PciLsGen4SetPg (Dbi, 0); + return MmioRead32 (Dbi + Offset); + } else { + // If Offset > 3KB, paging mechanism is used + // Select page index and offset within the page + PciLsGen4SetPg (Dbi, OFFSET_TO_PAGE_IDX (Offset)); + return MmioRead32 (Dbi + OFFSET_TO_PAGE_ADDR (Offset)); + } +} + +/** + Function to write to LsGen4 PCIe controller config space + LsGen4 PCIe controller requires page number to be set + in Bridge Control Register(PAB) for offset > 3KB. + + @param Dbi GPEX host controller address + @param Offset Offset to read from + +**/ +STATIC inline VOID PciLsGen4Write32 ( + IN EFI_PHYSICAL_ADDRESS Dbi, + IN UINT32 Offset, + IN UINT32 Value + ) +{ + if (Offset < INDIRECT_ADDR_BNDRY) { + PciLsGen4SetPg (Dbi, 0); + MmioWrite32 (Dbi + Offset, Value); + } else { + PciLsGen4SetPg (Dbi, OFFSET_TO_PAGE_IDX (Offset)); + MmioWrite32 (Dbi + OFFSET_TO_PAGE_ADDR (Offset), Value); + } +} #endif diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index 9fae19095cba..8e39fb25f83e 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -201,7 +201,11 @@ PcieLinkUp ( UINT32 State; UINT32 LtssmMask; =20 - LtssmMask =3D 0x3f; + if (PCI_LS_GEN4_CTRL) { + LtssmMask =3D 0x7f; + } else { + LtssmMask =3D 0x3f; + } =20 PcieOps =3D GetMmioOperations (FeaturePcdGet (PcdPciLutBigEndian)); State =3D PcieOps->Read32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) & L= tssmMask; @@ -237,38 +241,58 @@ PcieOutboundSet ( IN UINT64 Size ) { - // PCIe Layerscape : Outbound Window - MmioWrite32 (Dbi + IATU_VIEWPORT_OFF, - (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx)); + UINT32 Val; =20 - MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0, - (UINT32)Phys); - - MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0, - (UINT32)(Phys >> 32)); - - MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0, - (UINT32)(Phys + Size - BIT0)); - - MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0, - (UINT32)BusAddr); - - MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0, - (UINT32)(BusAddr >> 32)); - - MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0, - (UINT32)Type); - - if (CFG_SHIFT_ENABLE && - ((Type =3D=3D IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0) || - (Type =3D=3D IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1))) { - MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, - (IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | - IATU_ENABLE_CFG_SHIFT_FEATURE) - ); + if (PCI_LS_GEN4_CTRL) { + // PCIe Layerscape Gen4: Outbound Window + Size =3D ~(Size -1 ); + Val =3D PciLsGen4Read32 ((UINTN)Dbi, PAB_AXI_AMAP_CTRL (Idx)); + Val &=3D ~((AXI_AMAP_CTRL_TYPE_MASK << AXI_AMAP_CTRL_TYPE_SHIFT) | + (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT) | + AXI_AMAP_CTRL_EN); + Val |=3D ((Type & AXI_AMAP_CTRL_TYPE_MASK) << AXI_AMAP_CTRL_TYPE_SHIFT= ) | + (((UINT32)Size >> AXI_AMAP_CTRL_SIZE_SHIFT) << + AXI_AMAP_CTRL_SIZE_SHIFT) | AXI_AMAP_CTRL_EN; + PciLsGen4Write32 ((UINTN)Dbi, PAB_AXI_AMAP_CTRL (Idx), Val); + PciLsGen4Write32 ((UINTN)Dbi, PAB_AXI_AMAP_AXI_WIN (Idx), (UINT32)Phys= ); + PciLsGen4Write32 ((UINTN)Dbi, PAB_EXT_AXI_AMAP_AXI_WIN (Idx), Phys >> = 32); + PciLsGen4Write32 ((UINTN)Dbi, PAB_AXI_AMAP_PEX_WIN_L (Idx), (UINT32)Bu= sAddr); + PciLsGen4Write32 ((UINTN)Dbi, PAB_AXI_AMAP_PEX_WIN_H (Idx), BusAddr >>= 32); + PciLsGen4Write32 ((UINTN)Dbi, PAB_EXT_AXI_AMAP_SIZE (Idx), Size >> 32)= ; } else { - MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, - IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN); + // PCIe Layerscape : Outbound Window + MmioWrite32 (Dbi + IATU_VIEWPORT_OFF, + (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx)); + + MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0, + (UINT32)Phys); + + MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0, + (UINT32)(Phys >> 32)); + + MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0, + (UINT32)(Phys + Size - BIT0)); + + MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0, + (UINT32)BusAddr); + + MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0, + (UINT32)(BusAddr >> 32)); + + MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0, + (UINT32)Type); + + if (CFG_SHIFT_ENABLE && + ((Type =3D=3D IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0) || + (Type =3D=3D IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1))) { + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, + (IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | + IATU_ENABLE_CFG_SHIFT_FEATURE) + ); + } else { + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN); + } } } =20 @@ -373,6 +397,116 @@ PcieLsSetupAtu ( SEG_IO_SIZE ); } + +/** + Function to set-up ATU windows for PCIe LayerscapeGen4 controller + + @param Pcie Address of PCIe host controller + @param Cfg0Base PCIe controller phy address Type0 Configuration Space. + @param Cfg1Base PCIe controller phy address Type1 Configuration Space. + @param MemBase PCIe controller phy address Memory Space. + @param Mem64Base PCIe controller phy address MMIO64 Space. + @param IoBase PCIe controller phy address IO Space. +**/ +STATIC +VOID +PcieLsGen4SetupAtu ( + IN EFI_PHYSICAL_ADDRESS Pcie, + IN EFI_PHYSICAL_ADDRESS Cfg0Base, + IN EFI_PHYSICAL_ADDRESS Cfg1Base, + IN EFI_PHYSICAL_ADDRESS MemBase, + IN EFI_PHYSICAL_ADDRESS Mem64Base, + IN EFI_PHYSICAL_ADDRESS IoBase + ) +{ + UINT64 Mem64End; + UINT32 Index; + + Index=3D0; + + // ATU : OUTBOUND WINDOW 1 : CFG0 + PcieOutboundSet (Pcie, Index++, + PAB_AXI_TYPE_CFG, + Cfg0Base, + SEG_CFG_BUS, + SEG_CFG_SIZE); + + // ATU : OUTBOUND WINDOW 2 : IO + PcieOutboundSet (Pcie, Index++, + PAB_AXI_TYPE_IO, + IoBase, + SEG_IO_BUS, + SEG_IO_SIZE); + + // ATU : OUTBOUND WINDOW 3 : MEM + PcieOutboundSet (Pcie, Index++, + PAB_AXI_TYPE_MEM, + MemBase, + SEG_MEM_BUS, + SEG_MEM_SIZE); + + // + // To allow maximum MMIO64 space, MMIO64 window + // size must be multiple of max iATU size (4GB) + // + ASSERT ((PCI_MMIO64_WIN_SIZE & (SIZE_4GB - 1)) =3D=3D 0); + + Mem64End =3D Mem64Base + PCI_MMIO64_WIN_SIZE - 1; + while (Mem64Base < Mem64End) { + // ATU : OUTBOUND WINDOW : MMIO64 + PcieOutboundSet (Pcie, Index++, + PAB_AXI_TYPE_MEM, + Mem64Base, + Mem64Base, + SIZE_4GB); + + Mem64Base +=3D SIZE_4GB; + } +} + +/** + Function to set-up PCIe inbound window + + @param Pcie Address of PCIe host controller. + @param Idx Index of inbound window. + @param Type Type(Cfg/Mem/IO) of iATU outbound window. + @param Phys PCIe controller phy address for inbound window. + @param BusAdr PCIe controller bus address for inbound window. + @param Size Window size + +**/ + +STATIC +VOID +PciSetupInBoundWin ( + IN EFI_PHYSICAL_ADDRESS Pcie, + IN UINT32 Idx, + IN UINT32 Type, + IN UINT64 Phys, + IN UINT64 BusAddr, + IN UINT64 Size) +{ + UINT32 Val; + UINT64 WinSize; + + if (PCI_LS_GEN4_CTRL) { + Val =3D PciLsGen4Read32 ((UINTN)Pcie, PAB_PEX_AMAP_CTRL(Idx)); + Val &=3D ~(PEX_AMAP_CTRL_TYPE_MASK << PEX_AMAP_CTRL_TYPE_SHIFT); + Val &=3D ~(PEX_AMAP_CTRL_EN_MASK << PEX_AMAP_CTRL_EN_SHIFT); + Val =3D (Val | (Type << PEX_AMAP_CTRL_TYPE_SHIFT)); + Val =3D (Val | (1 << PEX_AMAP_CTRL_EN_SHIFT)); + + WinSize =3D ~(Size - 1); + PciLsGen4Write32 ((UINTN)Pcie, PAB_PEX_AMAP_CTRL(Idx), + (Val | (UINT32)WinSize)); + PciLsGen4Write32 ((UINTN)Pcie, PAB_EXT_PEX_AMAP_SIZE(Idx), (WinSize>>3= 2)); + PciLsGen4Write32 ((UINTN)Pcie, PAB_PEX_AMAP_AXI_WIN(Idx), (UINT32)Phys= ); + PciLsGen4Write32 ((UINTN)Pcie, PAB_EXT_PEX_AMAP_AXI_WIN(Idx), (Phys>>3= 2)); + PciLsGen4Write32 ((UINTN)Pcie, PAB_PEX_AMAP_PEX_WIN_L(Idx), (UINT32)Bu= sAddr); + PciLsGen4Write32 ((UINTN)Pcie, PAB_PEX_AMAP_PEX_WIN_H(Idx), (BusAddr >= >32)); + } +} + /** Helper function to set-up PCIe controller =20 @@ -397,16 +531,47 @@ PcieSetupCntrl ( { UINT32 Val; =20 - // PCIe Layerscape Controller Setup - PcieLsSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, Mem64Base, IoBase); - - // Program Class code for Layerscape PCIe controller - MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, 1); - Val =3D MmioRead32 ((UINTN)Pcie + PCI_CLASS_DEVICE); - Val &=3D ~(CLASS_CODE_MASK << CLASS_CODE_SHIFT); - Val |=3D (PCI_CLASS_BRIDGE_PCI << CLASS_CODE_SHIFT); - MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, Val); - MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, 0); + if (PCI_LS_GEN4_CTRL) { + // PCIe LsGen4 Controller Setup + + //Fix Class Code + Val =3D PciLsGen4Read32 ((UINTN)Pcie, GPEX_CLASSCODE); + Val &=3D ~(GPEX_CLASSCODE_MASK << GPEX_CLASSCODE_SHIFT); + Val |=3D PCI_CLASS_BRIDGE_PCI << GPEX_CLASSCODE_SHIFT; + PciLsGen4Write32 ((UINTN)Pcie, GPEX_CLASSCODE, Val); + + // Enable APIO and Memory/IO/CFG Windows + Val =3D PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_PIO_CTRL (0)); + Val |=3D APIO_EN | MEM_WIN_EN | IO_WIN_EN | CFG_WIN_EN; + PciLsGen4Write32 ((UINTN)Pcie, PAB_AXI_PIO_CTRL (0), Val); + + // LsGen4 Inbound Window Setup + PciSetupInBoundWin (Pcie, 0, PAB_AXI_TYPE_MEM, 0 , 0, SIZE_1TB); + + // LsGen4 Outbound Window Setup + PcieLsGen4SetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, Mem64Base, IoBa= se); + + // Enable AMBA & PEX PIO + Val =3D PciLsGen4Read32 ((UINTN)Pcie, PAB_CTRL); + Val |=3D PAB_CTRL_APIO_EN | PAB_CTRL_PPIO_EN; + PciLsGen4Write32 ((UINTN)Pcie, PAB_CTRL, Val); + + Val =3D PciLsGen4Read32 ((UINTN)Pcie, PAB_PEX_PIO_CTRL(0)); + Val |=3D PPIO_EN; + PciLsGen4Write32 ((UINTN)Pcie, PAB_PEX_PIO_CTRL(0), Val); + + } else { + // PCIe Layerscape Controller Setup + PcieLsSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, Mem64Base, IoBase); + + // Program Class code for Layerscape PCIe controller + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, 1); + Val =3D MmioRead32 ((UINTN)Pcie + PCI_CLASS_DEVICE); + Val &=3D ~(CLASS_CODE_MASK << CLASS_CODE_SHIFT); + Val |=3D (PCI_CLASS_BRIDGE_PCI << CLASS_CODE_SHIFT); + MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, Val); + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, 0); + } } =20 /** --=20 2.7.4