[PATCH edk2-platforms v2 06/16] Silicon/NXP: PciHostBridgeLib: add Workaround for A-011451

[Wasim Khan <wasim.khan@oss.nxp.com>]

From: Wasim Khan <wasim.khan@nxp.com>

When PCIe Layerscape Gen4 controller is sending multiple split
completions and ACK latency expires indicating that ACK should
be send at priority. But because of large number of split completions
and FC update DLLP,the controller does not give priority to ACK
transmission. This results into ACK latency timer timeout error
at the link partner and the pending TLPs are replayed by the
link partner again.

Workaround:
Reduce the ACK latency timeout value.

Co-authored-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Co-authored-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---

Notes:
    V2:
    - Removed Signed-off and added Co-authored-by for co-author

 Silicon/NXP/Include/Pcie.h                              | 4 ++++
 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 6 ++++++
 2 files changed, 10 insertions(+)

diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h
index b7d46f3a3bd2..210e4c3cf5e7 100755
--- a/Silicon/NXP/Include/Pcie.h
+++ b/Silicon/NXP/Include/Pcie.h
@@ -202,4 +202,8 @@ STATIC inline VOID PciLsGen4Write32 (
     MmioWrite32 (Dbi + OFFSET_TO_PAGE_ADDR (Offset), Value);
   }
 }
+
+#define GPEX_ACK_REPLAY_TO                      0x438
+#define ACK_LAT_TO_VAL_SHIFT                    0
+#define ACK_LAT_TO_VAL_MASK                     0x1fff
 #endif
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 8e39fb25f83e..339a3d9bffa6 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -534,6 +534,12 @@ PcieSetupCntrl (
   if (PCI_LS_GEN4_CTRL) {
     // PCIe LsGen4 Controller Setup
 
+    // Workaround for A-011451
+    Val = PciLsGen4Read32 ((UINTN)Pcie, GPEX_ACK_REPLAY_TO);
+    Val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
+    Val |= (4 << ACK_LAT_TO_VAL_SHIFT);
+    PciLsGen4Write32 ((UINTN)Pcie, GPEX_ACK_REPLAY_TO, Val);
+
     //Fix Class Code
     Val = PciLsGen4Read32 ((UINTN)Pcie, GPEX_CLASSCODE);
     Val &= ~(GPEX_CLASSCODE_MASK << GPEX_CLASSCODE_SHIFT);
-- 
2.7.4