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X-MS-Exchange-AntiSpam-MessageData: cBe3zAEjSLNcjFDeFjc7intuDWabIqp+IhxweZ6/++y/gX8VuFW+rsNaP4sh+WdElaJDVS1Fcm1SNdpgjU/DR0Bxg6cpQ7BnRyPI5aLSlyGhQiJA6WsKpBHhIkbgdyb64ajMeWQ92IO/KXrk09ImskwzquaQii0MTWPpRczqUR5OhjBA55EQxIUc5jMStTSH8vPhioLTRZB5YYI05P4ay3oTaUoIgsWncb+GAyOtiOR2L8vi01Yhx9K/pYEpgq25pwf8+CgnaoblbJD75q8hmXrUYcOrqnMs1KaBC08A3AYqthHW2phuRnMvJ5oAhi/2ddhWpX+C0/omKTdOmViiRPYJsI6iHGvmhx1uUudhDTN5VUAS2iO1CqXm2Hu5bZoliA9y3Rz1CmlXU2L9ZfN+4JM7cMksWj8b5KKxAQgknph07PhDV0L5KPzyVUO2uAWTwNNBGXfionlwXnsMBWwzSg46V/gmjAYzeHqQswZLL6s= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: aa8edf30-205e-43af-3d4c-08d801502ce8 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2020 08:38:34.9715 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZwQV65KT8J3kKc4qSG0FLRY+ZWwL1t5DKDoArAVI8fXwy+tYoOSjPMSh7/8Tfkab+xX25x6PpemCtcnaXjAtgA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6367 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Wasim Khan Dump ATU windows for PCIe LsGen4 controller. Co-authored-by: Vabhav Sharma Co-authored-by: Wasim Khan Signed-off-by: Wasim Khan --- Notes: V2: - Removed Signed-off and added Co-authored-by for co-author - Drop PcdPciDebug and use DEBUG_CODE_BEGIN/DEBUG_CODE_END - Passing Max window number as argument to LsGen4DumpAtu() Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 36 +++++++++++++= +++++++ 1 file changed, 36 insertions(+) diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index 339a3d9bffa6..53b93e2b6f23 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -399,6 +399,38 @@ PcieLsSetupAtu ( } =20 /** + Dump PCIe LsGen4 ATU + + @param Pcie Address of PCIe host controller. + @param Count Number of Windows +**/ +VOID LsGen4DumpAtu ( + IN EFI_PHYSICAL_ADDRESS Pcie, + IN UINT32 Count + ) +{ + UINT32 Cnt; + for (Cnt =3D 0; Cnt < Count; Cnt++) { + DEBUG ((DEBUG_INFO,"APIO WINDOW%d:\n", Cnt)); + DEBUG ((DEBUG_INFO,"\tLOWER PHYS 0x%08x\n", + PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_AXI_WIN (Cnt)))); + DEBUG ((DEBUG_INFO,"\tUPPER PHYS 0x%08x\n", + PciLsGen4Read32 ((UINTN)Pcie, PAB_EXT_AXI_AMAP_AXI_WIN (Cnt)))= ); + DEBUG ((DEBUG_INFO,"\tLOWER BUS 0x%08x\n", + PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_PEX_WIN_L (Cnt)))); + DEBUG ((DEBUG_INFO,"\tUPPER BUS 0x%08x\n", + PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_PEX_WIN_H (Cnt)))); + DEBUG ((DEBUG_INFO,"\tSIZE 0x%08x\n", + PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_CTRL (Cnt)) & + (AXI_AMAP_CTRL_SIZE_MASK << AXI_AMAP_CTRL_SIZE_SHIFT))); + DEBUG ((DEBUG_INFO,"\tEXT_SIZE 0x%08x\n", + PciLsGen4Read32 ((UINTN)Pcie, PAB_EXT_AXI_AMAP_SIZE (Cnt)))); + DEBUG ((DEBUG_INFO,"\tCTRL: 0x%08x\n", + PciLsGen4Read32 ((UINTN)Pcie, PAB_AXI_AMAP_CTRL (Cnt)))); + } +} + +/** Function to set-up ATU windows for PCIe LayerscapeGen4 controller =20 @param Pcie Address of PCIe host controller @@ -462,6 +494,10 @@ PcieLsGen4SetupAtu ( =20 Mem64Base +=3D SIZE_4GB; } + + DEBUG_CODE_BEGIN (); + LsGen4DumpAtu (Pcie, Index); + DEBUG_CODE_END (); } =20 /** --=20 2.7.4