[PATCH edk2-platforms v2 08/16] Silicon/NXP: PciHostBridgeLib: Dump Layerscale iATU windows

[Wasim Khan <wasim.khan@oss.nxp.com>]

From: Wasim Khan <wasim.khan@nxp.com>

Dump ATU windows for PCIe Layerscape controller.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---

Notes:
    V2:
    - Drop PcdPciDebug and use DEBUG_CODE_BEGIN/DEBUG_CODE_END
    - Passing Max window number as argument to LsDumpAtu()

 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 44 ++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 53b93e2b6f23..670353b6c8d4 100644
--- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -297,6 +297,46 @@ PcieOutboundSet (
 }
 
 /**
+  Dump PCIe Layerscape ATU
+
+  @param Pcie     Address of PCIe host controller.
+  @param Count    Number of Windows
+**/
+VOID LsDumpAtu (
+  IN EFI_PHYSICAL_ADDRESS Pcie,
+  IN UINT32 Count
+  )
+{
+  UINT32 Cnt;
+  for (Cnt = 0; Cnt < Count; Cnt++) {
+    MmioWrite32 ((UINTN)Pcie + IATU_VIEWPORT_OFF,
+                  (UINT32)(IATU_VIEWPORT_OUTBOUND | Cnt));
+
+    DEBUG ((DEBUG_INFO, "iATU%d:\n",Cnt));
+    DEBUG ((DEBUG_INFO, "\tLOWER PHYS 0x%08x\n",
+            MmioRead32 ((UINTN)Pcie + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0)));
+
+    DEBUG ((DEBUG_INFO, "\tUPPER PHYS 0x%08x\n",
+            MmioRead32 ((UINTN)Pcie + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0)));
+
+    DEBUG ((DEBUG_INFO, "\tLOWER BUS 0x%08x\n",
+            MmioRead32 ((UINTN)Pcie + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0)));
+
+    DEBUG ((DEBUG_INFO, "\tUPPER BUS 0x%08x\n",
+            MmioRead32 ((UINTN)Pcie + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0)));
+
+    DEBUG ((DEBUG_INFO, "\tLIMIT     0x%08x\n",
+            MmioRead32 ((UINTN)Pcie + IATU_LIMIT_ADDR_OFF_OUTBOUND_0)));
+
+    DEBUG ((DEBUG_INFO, "\tCR1       0x%08x\n",
+            MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_1_OFF_OUTBOUND_0)));
+
+    DEBUG ((DEBUG_INFO, "\tCR2       0x%08x\n",
+            MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_2_OFF_OUTBOUND_0)));
+  }
+}
+
+/**
   Function to set-up iATU windows for Layerscape PCIe controller
 
   @param Pcie      Address of PCIe host controller
@@ -396,6 +436,10 @@ PcieLsSetupAtu (
     SEG_IO_BUS,
     SEG_IO_SIZE
     );
+
+  DEBUG_CODE_BEGIN ();
+  LsDumpAtu (Pcie, Index);
+  DEBUG_CODE_END ();
 }
 
 /**
-- 
2.7.4