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X-MS-Exchange-AntiSpam-MessageData: BcA4+6zMr9Tjdk2it9f7NWEafCQWS6jPg1SIj9GrFuBXd/Fq/Rq5pwwrh+ZtCYe+tuHDUcJPQk/PQpuXziSriMdMhXUqp1gUVvHxuwSlzICFE3xx7ZYgUJXNmlW5p6rvoKuEKBKgsmTu6FiFcaBQv3HCPkzq3IsAHDDq0KmzHtnW/gP6odUuSHkprSz3TFcTv0/4YecxYotTrcSAa+mn8Z36O4yPT3UBn9d32YQAQmikDhUsFkh42hT4xWw98o1OEuPkvl4VrZtM1R1Hjq6RGRDGI4QszOaFHqDj/gSRdemmiTyflPHwZRnAU8ricguha7bZniCWHtjelP3L6XDT5pJUQF/zVNAzQbWYHDd8As89njrjVtcQwJIFladuvBFkdWq03NeFXfT0rhKfJxbaXwYrjDusqf3urWnQV6IejYLt+OS/b9CxRreheLAWWT0l5hHsD6OK3kfcLTvG7rj5V1PqF2af0A80Jx5MFklFNjQ= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 584f1a71-51f1-459d-0d82-08d80661e9eb X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2020 19:28:08.2293 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XiN/9k9KLICG11ozK8tH5pPt92n0LNA7Ci5DHJdbFxpXQu2WLLdNO+IgiG/BbaBTHt1m2+GJy/lWwc0oFVRp/A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6768 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Wasim Khan Based on the serdes protocol value in reset configuration word (RCW), different PCIe controllers are enabled. Get serdes protocol map and initialize only enabled PCIe controllers. Signed-off-by: Wasim Khan --- Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 + Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 +++++++++++= ++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Si= licon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf index aa5a9dec7c34..6003da708698 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -28,6 +28,7 @@ [LibraryClasses] IoAccessLib MemoryAllocationLib PcdLib + SocLib =20 [FeaturePcd] gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index 549f4fa133fb..323afc2015ae 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -719,6 +720,32 @@ PcieSetupCntrl ( } =20 /** + This function checks whether PCIe is enabled or not + depending upon SoC serdes protocol map + + @param PcieNum PCIe number. + + @return The PCIe number enabled in map. + @return FALSE PCIe number is disabled in map. + +**/ +STATIC +BOOLEAN +IsPcieNumEnabled( + IN UINTN PcieNum + ) +{ + UINT64 SerDesProtocolMap; + + SerDesProtocolMap =3D 0x0; + + // Reading serdes protocol map + GetSerdesProtocolMaps (&SerDesProtocolMap); + + return (SerDesProtocolMap & (0x1u << (PcieNum))) !=3D 0 ; +} + +/** Return all the root bridge instances in an array. =20 @param Count Return the count of root bridge instances. @@ -750,13 +777,19 @@ PciHostBridgeGetRootBridges ( PciPhyIoAddr [Idx] =3D PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx); Regs[Idx] =3D PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); =20 + // Check is the PCIe controller is enabled + if (IsPcieNumEnabled (Idx + 1) =3D=3D 0) { + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx is disabled \n", Idx + 1, Re= gs[Idx])); + continue; + } + // Check PCIe Link LinkUp =3D PcieLinkUp(Regs[Idx], Idx); =20 if (!LinkUp) { continue; } - DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + 1)); + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx :Passed Linkup Phase\n", Idx += 1, Regs[Idx])); // Set up PCIe Controller and ATU windows PcieSetupCntrl (Regs[Idx], PciPhyCfg0Addr[Idx], --=20 2.7.4