From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.13452.1591276338108461755 for ; Thu, 04 Jun 2020 06:12:18 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: vijayenthiran.subramaniam@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C6CCC30E; Thu, 4 Jun 2020 06:12:17 -0700 (PDT) Received: from usa.arm.com (a074939-lin.blr.arm.com [10.162.16.84]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 837DE3F305; Thu, 4 Jun 2020 06:12:15 -0700 (PDT) From: "Vijayenthiran Subramaniam" To: devel@edk2.groups.io, leif@nuviainc.com, Ard.Biesheuvel@arm.com Cc: thomas.abraham@arm.com, Sami.Mujawar@arm.com, richard.storer@arm.com Subject: [PATCH] ArmPkg/ArmSvcLib: prevent speculative execution beyond svc Date: Thu, 4 Jun 2020 18:42:09 +0530 Message-Id: <1591276329-20607-1-git-send-email-vijayenthiran.subramaniam@arm.com> X-Mailer: git-send-email 2.7.4 Supervisor Call instruction (SVC) is used by the Arm Standalone MM environment to request services from the privileged software (such as ARM Trusted Firmware running in EL3) and also return back to the non-secure caller via EL3. Some Arm CPUs speculatively executes the instructions after the SVC instruction without crossing the privilege level (S-EL0). Although the results of this execution are architecturally discarded, adversary running on the non-secure side can manipulate the contents of the general purpose registers to leak the secure work memory through spectre like micro-architectural side channel attacks. This behavior is demonstrated by the SafeSide project [1] and [2]. Add barrier instructions after SVC to prevent speculative execution to mitigate such attacks. [1]: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc [2]: https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Vijayenthiran Subramaniam --- ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S | 5 ++++- ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.S | 5 ++++- ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm | 5 ++++- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S b/ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S index 7c94db3451f0..ee265f94b960 100644 --- a/ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S +++ b/ArmPkg/Library/ArmSvcLib/AArch64/ArmSvc.S @@ -1,5 +1,5 @@ // -// Copyright (c) 2012 - 2017, ARM Limited. All rights reserved. +// Copyright (c) 2012 - 2020, ARM Limited. All rights reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent // @@ -25,6 +25,9 @@ ASM_PFX(ArmCallSvc): ldp x0, x1, [x0, #0] svc #0 + // Prevent speculative execution beyond svc instruction + dsb nsh + isb // Pop the ARM_SVC_ARGS structure address from the stack into x9 ldr x9, [sp, #16] diff --git a/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.S b/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.S index fc2886b6b53e..e81eb88f2e87 100644 --- a/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.S +++ b/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.S @@ -1,5 +1,5 @@ // -// Copyright (c) 2016 - 2017, ARM Limited. All rights reserved. +// Copyright (c) 2016 - 2020, ARM Limited. All rights reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent // @@ -18,6 +18,9 @@ ASM_PFX(ArmCallSvc): ldm r0, {r0-r7} svc #0 + // Prevent speculative execution beyond svc instruction + dsb nsh + isb // Load the ARM_SVC_ARGS structure address from the stack into r8 ldr r8, [sp] diff --git a/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm b/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm index 82d10c023ae3..d1751488b2b1 100644 --- a/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm +++ b/ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm @@ -1,5 +1,5 @@ // -// Copyright (c) 2016 - 2017, ARM Limited. All rights reserved. +// Copyright (c) 2016 - 2020, ARM Limited. All rights reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent // @@ -16,6 +16,9 @@ ldm r0, {r0-r7} svc #0 + // Prevent speculative execution beyond svc instruction + dsb nsh + isb // Load the ARM_SVC_ARGS structure address from the stack into r8 ldr r8, [sp] -- 2.7.4