* [PATCH edk2-platforms v2 0/3] Add SerDes Support
@ 2020-06-07 13:15 Wasim Khan
2020-06-07 13:15 ` [PATCH edk2-platforms v2 1/3] Silicon/NXP/Library: Implement SerDesHelperLib Wasim Khan
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Wasim Khan @ 2020-06-07 13:15 UTC (permalink / raw)
To: devel, meenakshi.aggarwal, V.Sethi, ard.biesheuvel, leif; +Cc: Wasim Khan
From: Wasim Khan <wasim.khan@nxp.com>
NXP SoCs supports different Serdes protocols using reset
configuration word (RCW).
Based on Serdes protocol value in reset configuration word (RCW)
different IP blocks gets enabled in HW.
This patch series implements SerDesHelperLib and provide SoC specific
serdes configuration for LS1043A, which can be used by different IPs
(Ex: PCIe) to know the enabled interfaces and perform the required
initialization.
V1 Series can be referred here:
https://edk2.groups.io/g/devel/message/60542
Changes in V2:
- Addressed review comments received on V1.
Wasim Khan (3):
Silicon/NXP/Library: Implement SerDesHelperLib
Silicon/NXP: LS1043A: Add SerDes Support
Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe
controllers
Silicon/NXP/NxpQoriqLs.dec | 1 +
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 +
Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf | 6 +
Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 +
Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf | 28 ++++
Silicon/NXP/Include/Library/SerDes.h | 28 ++++
Silicon/NXP/Include/Library/SerDesHelperLib.h | 64 ++++++++
Silicon/NXP/LS1043A/Library/SocLib/SerDes.c | 132 ++++++++++++++++
Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 ++++-
Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c | 164 ++++++++++++++++++++
10 files changed, 460 insertions(+), 1 deletion(-)
create mode 100644 Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf
create mode 100644 Silicon/NXP/Include/Library/SerDes.h
create mode 100644 Silicon/NXP/Include/Library/SerDesHelperLib.h
create mode 100644 Silicon/NXP/LS1043A/Library/SocLib/SerDes.c
create mode 100644 Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c
--
2.7.4
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH edk2-platforms v2 1/3] Silicon/NXP/Library: Implement SerDesHelperLib 2020-06-07 13:15 [PATCH edk2-platforms v2 0/3] Add SerDes Support Wasim Khan @ 2020-06-07 13:15 ` Wasim Khan 2020-06-08 15:12 ` Leif Lindholm 2020-06-07 13:15 ` [PATCH edk2-platforms v2 2/3] Silicon/NXP: LS1043A: Add SerDes Support Wasim Khan 2020-06-07 13:15 ` [PATCH edk2-platforms v2 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers Wasim Khan 2 siblings, 1 reply; 8+ messages in thread From: Wasim Khan @ 2020-06-07 13:15 UTC (permalink / raw) To: devel, meenakshi.aggarwal, V.Sethi, ard.biesheuvel, leif; +Cc: Wasim Khan From: Wasim Khan <wasim.khan@nxp.com> Implement SerDesHelperLib to provide helper functions which can be used for SoC specific SerDes configuration. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> --- Notes: Changes in V2: - Addressed review comments for structure, variable and function names - Using BIT0 instead of 0x1u Silicon/NXP/NxpQoriqLs.dec | 1 + Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf | 28 ++++ Silicon/NXP/Include/Library/SerDesHelperLib.h | 64 ++++++++ Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c | 164 ++++++++++++++++++++ 4 files changed, 257 insertions(+) diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index d4d3057af509..d09a1ae194be 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -35,6 +35,7 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x00000501 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x00000502 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x00000503 + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes|0x0|UINT8|0x00000504 [PcdsDynamic.common] gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600 diff --git a/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf new file mode 100644 index 000000000000..7a781620e449 --- /dev/null +++ b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf @@ -0,0 +1,28 @@ +## @file +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SerDesHelperLib + FILE_GUID = 2930e932-a700-41e8-80f9-f1a2dedd2c4f + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SerDesHelperLib + +[Packages] + MdePkg/MdePkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + DebugLib + PcdLib + +[Sources.common] + SerDesHelperLib.c + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes diff --git a/Silicon/NXP/Include/Library/SerDesHelperLib.h b/Silicon/NXP/Include/Library/SerDesHelperLib.h new file mode 100644 index 000000000000..377f020e0b3a --- /dev/null +++ b/Silicon/NXP/Include/Library/SerDesHelperLib.h @@ -0,0 +1,64 @@ +/** SerDesHelperLib.h + The Header file for SerDesHelperLib + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef SERDES_HELPER_LIB_H +#define SERDES_HELPER_LIB_H + +#include <Uefi.h> +#include <Library/SerDes.h> + +typedef struct { + UINT16 Protocol; + UINT8 SerDesLane[FixedPcdGet8 (PcdSerDesLanes)]; +} SERDES_CONFIG; + +typedef enum { + SERDES_1 = 0, + SERDES_2, + SERDES_3, + SERDES_MAX +} SERDES_NUMBER; + +UINT32 +GetSerDesProtocol ( + IN INTN SerDes, + IN INTN SerDesProtocol, + IN INTN Lane, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config + ); + +EFI_STATUS +IsSerDesProtocolValid ( + IN INTN SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN SERDES_CONFIG *Config + ); + +EFI_STATUS +GetSerDesMap ( + IN UINT32 SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config, + OUT UINT64 *SerDesProtocolMap + ); + +VOID +SerDesInstanceProbeLanes ( + IN UINT32 SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config, + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ); +#endif diff --git a/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c new file mode 100644 index 000000000000..52c27a0fd49d --- /dev/null +++ b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c @@ -0,0 +1,164 @@ +/** SerDes.c + Provides SoC specific SerDes interface + + Copyright 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Library/DebugLib.h> +#include <Library/SerDesHelperLib.h> + +/** + Function to get SerDes Lane protocol corresponding to + SerDes protocol. + + @param SerDes SerDes number. + @param SerDesProtocol SerDes protocol number. + @param Lane SerDes Lane number. + @param SerDesMaxProtocol Max SerDes protocol number. + @param Config SerDes Configuration. + + @return SerDes Lane protocol. + +**/ +UINT32 +GetSerDesProtocol ( + IN INTN SerDes, + IN INTN SerDesProtocol, + IN INTN Lane, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config + ) +{ + while (Config->Protocol) { + if (Config->Protocol == SerDesProtocol) { + return Config->SerDesLane[Lane]; + } + Config++; + } + + return SerDesMaxProtocol; +} + +/** + Function to validate input SerDes protocol. + + @param SerDes SerDes number. + @param SerDesProtocol SerDes protocol number. + @param SerDesNumLanes Number of SerDes Lanes. + @param Config SerDes Configuration. + + @return EFI_NOT_FOUND SerDes Protocol not a valid protocol. + @return EFI_SUCCESS SerDes Protocol is a valid protocol. + +**/ +EFI_STATUS +IsSerDesProtocolValid ( + IN INTN SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN SERDES_CONFIG *Config + ) +{ + UINT8 Count; + + while (Config->Protocol) { + if (Config->Protocol == SerDesProtocol) { + DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", SerDesProtocol)); + break; + } + Config++; + } + + if (!Config->Protocol) { + return EFI_NOT_FOUND; + } + + for (Count = 0; Count < SerDesNumLanes; Count++) { + if (Config->SerDesLane[Count] != 0) { + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} + +/** + Get Lane protocol on provided SerDes Lane and execute callback function. + + @param SerDes SerDes number. + @param SerDesProtocol SerDes protocol number. + @param SerDesNumLanes Number of SerDes Lanes. + @param SerDesMaxProtocol Max SerDes protocol number. + @param Config SerDes Configuration. + @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol + @param Arg Pointer to Arguments to be passed to callback function. +**/ +VOID +SerDesInstanceProbeLanes ( + IN UINT32 SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config, + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + INT8 Lane; + UINT32 LaneProtocol; + + // Invoke callback for all lanes in the SerDes instance: + for (Lane = 0; Lane < SerDesNumLanes; Lane++) { + LaneProtocol = GetSerDesProtocol (SerDes, SerDesProtocol, Lane, SerDesMaxProtocol, Config); + ASSERT (LaneProtocol < SerDesMaxProtocol); + if (LaneProtocol != 0x0) { + SerDesLaneProbeCallback (LaneProtocol, Arg); + } + } +} + +/** + Function to fill SerDes map information. + + @param SerDes SerDes number. + @param SerDesProtocol SerDes protocol number. + @param SerDesNumLanes Number of SerDes Lanes. + @param SerDesMaxProtocol Max SerDes protocol number. + @param Config SerDes Configuration. + @param SerDesProtocolMap Output SerDes protocol map of enabled devices. + +**/ +EFI_STATUS +GetSerDesMap ( + IN UINT32 SerDes, + IN UINT32 SerDesProtocol, + IN UINT8 SerDesNumLanes, + IN UINT32 SerDesMaxProtocol, + IN SERDES_CONFIG *Config, + OUT UINT64 *SerDesProtocolMap + ) +{ + INTN Lane; + EFI_STATUS Status; + UINT32 LanePrtcl; + + Status = IsSerDesProtocolValid (SerDes, SerDesProtocol, SerDesNumLanes, Config); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: SERDES%d[PRTCL] = 0x%x is not valid, Status = %r \n", + __FUNCTION__, SerDes + 1, SerDesProtocol, Status)); + return Status; + } + + for (Lane = 0; Lane < SerDesNumLanes; Lane++) { + LanePrtcl = GetSerDesProtocol (SerDes, SerDesProtocol, Lane, SerDesMaxProtocol, Config); + if (LanePrtcl >= SerDesMaxProtocol) { + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)); + return EFI_NO_MAPPING; + } + *SerDesProtocolMap |= (BIT0 << (LanePrtcl)); + } + + return EFI_SUCCESS; +} -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH edk2-platforms v2 1/3] Silicon/NXP/Library: Implement SerDesHelperLib 2020-06-07 13:15 ` [PATCH edk2-platforms v2 1/3] Silicon/NXP/Library: Implement SerDesHelperLib Wasim Khan @ 2020-06-08 15:12 ` Leif Lindholm 0 siblings, 0 replies; 8+ messages in thread From: Leif Lindholm @ 2020-06-08 15:12 UTC (permalink / raw) To: Wasim Khan; +Cc: devel, meenakshi.aggarwal, V.Sethi, ard.biesheuvel, Wasim Khan On Sun, Jun 07, 2020 at 18:45:48 +0530, Wasim Khan wrote: > From: Wasim Khan <wasim.khan@nxp.com> > > Implement SerDesHelperLib to provide helper functions which > can be used for SoC specific SerDes configuration. > > Signed-off-by: Wasim Khan <wasim.khan@nxp.com> > --- > > Notes: > Changes in V2: > - Addressed review comments for structure, variable and function names > - Using BIT0 instead of 0x1u > > Silicon/NXP/NxpQoriqLs.dec | 1 + > Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf | 28 ++++ > Silicon/NXP/Include/Library/SerDesHelperLib.h | 64 ++++++++ > Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c | 164 ++++++++++++++++++++ > 4 files changed, 257 insertions(+) > > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec > index d4d3057af509..d09a1ae194be 100644 > --- a/Silicon/NXP/NxpQoriqLs.dec > +++ b/Silicon/NXP/NxpQoriqLs.dec > @@ -35,6 +35,7 @@ [PcdsFixedAtBuild.common] > gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x00000501 > gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x00000502 > gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x00000503 > + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes|0x0|UINT8|0x00000504 > > [PcdsDynamic.common] > gNxpQoriqLsTokenSpaceGuid.PcdPciCfgShiftEnable|FALSE|BOOLEAN|0x00000600 > diff --git a/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf > new file mode 100644 > index 000000000000..7a781620e449 > --- /dev/null > +++ b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf > @@ -0,0 +1,28 @@ > +## @file > +# > +# Copyright 2020 NXP > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = SerDesHelperLib > + FILE_GUID = 2930e932-a700-41e8-80f9-f1a2dedd2c4f > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = SerDesHelperLib > + > +[Packages] > + MdePkg/MdePkg.dec > + Silicon/NXP/NxpQoriqLs.dec > + > +[LibraryClasses] > + DebugLib > + PcdLib > + > +[Sources.common] > + SerDesHelperLib.c > + > +[FixedPcd] > + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes > diff --git a/Silicon/NXP/Include/Library/SerDesHelperLib.h b/Silicon/NXP/Include/Library/SerDesHelperLib.h > new file mode 100644 > index 000000000000..377f020e0b3a > --- /dev/null > +++ b/Silicon/NXP/Include/Library/SerDesHelperLib.h > @@ -0,0 +1,64 @@ > +/** SerDesHelperLib.h > + The Header file for SerDesHelperLib > + > + Copyright 2020 NXP > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef SERDES_HELPER_LIB_H > +#define SERDES_HELPER_LIB_H > + > +#include <Uefi.h> > +#include <Library/SerDes.h> > + > +typedef struct { > + UINT16 Protocol; > + UINT8 SerDesLane[FixedPcdGet8 (PcdSerDesLanes)]; > +} SERDES_CONFIG; > + > +typedef enum { > + SERDES_1 = 0, > + SERDES_2, > + SERDES_3, > + SERDES_MAX > +} SERDES_NUMBER; > + > +UINT32 > +GetSerDesProtocol ( > + IN INTN SerDes, > + IN INTN SerDesProtocol, > + IN INTN Lane, > + IN UINT32 SerDesMaxProtocol, > + IN SERDES_CONFIG *Config > + ); > + > +EFI_STATUS > +IsSerDesProtocolValid ( > + IN INTN SerDes, > + IN UINT32 SerDesProtocol, > + IN UINT8 SerDesNumLanes, > + IN SERDES_CONFIG *Config > + ); > + > +EFI_STATUS > +GetSerDesMap ( > + IN UINT32 SerDes, > + IN UINT32 SerDesProtocol, > + IN UINT8 SerDesNumLanes, > + IN UINT32 SerDesMaxProtocol, > + IN SERDES_CONFIG *Config, > + OUT UINT64 *SerDesProtocolMap > + ); > + > +VOID > +SerDesInstanceProbeLanes ( > + IN UINT32 SerDes, > + IN UINT32 SerDesProtocol, > + IN UINT8 SerDesNumLanes, > + IN UINT32 SerDesMaxProtocol, > + IN SERDES_CONFIG *Config, > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > + IN VOID *Arg > + ); > +#endif > diff --git a/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c > new file mode 100644 > index 000000000000..52c27a0fd49d > --- /dev/null > +++ b/Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.c > @@ -0,0 +1,164 @@ > +/** SerDes.c > + Provides SoC specific SerDes interface > + > + Copyright 2020 NXP > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include <Library/DebugLib.h> > +#include <Library/SerDesHelperLib.h> > + > +/** > + Function to get SerDes Lane protocol corresponding to > + SerDes protocol. > + > + @param SerDes SerDes number. > + @param SerDesProtocol SerDes protocol number. > + @param Lane SerDes Lane number. > + @param SerDesMaxProtocol Max SerDes protocol number. > + @param Config SerDes Configuration. > + > + @return SerDes Lane protocol. > + > +**/ > +UINT32 > +GetSerDesProtocol ( > + IN INTN SerDes, > + IN INTN SerDesProtocol, > + IN INTN Lane, > + IN UINT32 SerDesMaxProtocol, > + IN SERDES_CONFIG *Config > + ) > +{ > + while (Config->Protocol) { > + if (Config->Protocol == SerDesProtocol) { > + return Config->SerDesLane[Lane]; > + } > + Config++; > + } > + > + return SerDesMaxProtocol; > +} > + > +/** > + Function to validate input SerDes protocol. > + > + @param SerDes SerDes number. > + @param SerDesProtocol SerDes protocol number. > + @param SerDesNumLanes Number of SerDes Lanes. > + @param Config SerDes Configuration. > + > + @return EFI_NOT_FOUND SerDes Protocol not a valid protocol. > + @return EFI_SUCCESS SerDes Protocol is a valid protocol. > + > +**/ > +EFI_STATUS > +IsSerDesProtocolValid ( > + IN INTN SerDes, > + IN UINT32 SerDesProtocol, > + IN UINT8 SerDesNumLanes, > + IN SERDES_CONFIG *Config > + ) > +{ > + UINT8 Count; > + > + while (Config->Protocol) { > + if (Config->Protocol == SerDesProtocol) { > + DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", SerDesProtocol)); > + break; > + } > + Config++; > + } > + > + if (!Config->Protocol) { > + return EFI_NOT_FOUND; > + } > + > + for (Count = 0; Count < SerDesNumLanes; Count++) { > + if (Config->SerDesLane[Count] != 0) { > + return EFI_SUCCESS; > + } > + } > + > + return EFI_NOT_FOUND; > +} > + > +/** > + Get Lane protocol on provided SerDes Lane and execute callback function. > + > + @param SerDes SerDes number. > + @param SerDesProtocol SerDes protocol number. > + @param SerDesNumLanes Number of SerDes Lanes. > + @param SerDesMaxProtocol Max SerDes protocol number. > + @param Config SerDes Configuration. > + @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol > + @param Arg Pointer to Arguments to be passed to callback function. > +**/ > +VOID > +SerDesInstanceProbeLanes ( > + IN UINT32 SerDes, > + IN UINT32 SerDesProtocol, > + IN UINT8 SerDesNumLanes, > + IN UINT32 SerDesMaxProtocol, > + IN SERDES_CONFIG *Config, > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > + IN VOID *Arg > + ) > +{ > + INT8 Lane; > + UINT32 LaneProtocol; > + > + // Invoke callback for all lanes in the SerDes instance: > + for (Lane = 0; Lane < SerDesNumLanes; Lane++) { > + LaneProtocol = GetSerDesProtocol (SerDes, SerDesProtocol, Lane, SerDesMaxProtocol, Config); > + ASSERT (LaneProtocol < SerDesMaxProtocol); > + if (LaneProtocol != 0x0) { > + SerDesLaneProbeCallback (LaneProtocol, Arg); > + } > + } > +} > + > +/** > + Function to fill SerDes map information. > + > + @param SerDes SerDes number. > + @param SerDesProtocol SerDes protocol number. > + @param SerDesNumLanes Number of SerDes Lanes. > + @param SerDesMaxProtocol Max SerDes protocol number. > + @param Config SerDes Configuration. > + @param SerDesProtocolMap Output SerDes protocol map of enabled devices. > + > +**/ > +EFI_STATUS > +GetSerDesMap ( > + IN UINT32 SerDes, > + IN UINT32 SerDesProtocol, > + IN UINT8 SerDesNumLanes, > + IN UINT32 SerDesMaxProtocol, > + IN SERDES_CONFIG *Config, > + OUT UINT64 *SerDesProtocolMap > + ) > +{ > + INTN Lane; > + EFI_STATUS Status; > + UINT32 LanePrtcl; Still some Prtcl left in this function. Other than that I'm happy with this. With that fixed: Reviewed-by: Leif Lindholm <leif@nuviainc.com> If that's the only comment I have on v2, I can fix that up before committing. If I ask for a v3 for 2 or 3/3, could you please include this update? > + > + Status = IsSerDesProtocolValid (SerDes, SerDesProtocol, SerDesNumLanes, Config); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "%a: SERDES%d[PRTCL] = 0x%x is not valid, Status = %r \n", > + __FUNCTION__, SerDes + 1, SerDesProtocol, Status)); > + return Status; > + } > + > + for (Lane = 0; Lane < SerDesNumLanes; Lane++) { > + LanePrtcl = GetSerDesProtocol (SerDes, SerDesProtocol, Lane, SerDesMaxProtocol, Config); > + if (LanePrtcl >= SerDesMaxProtocol) { > + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl)); > + return EFI_NO_MAPPING; > + } > + *SerDesProtocolMap |= (BIT0 << (LanePrtcl)); > + } > + > + return EFI_SUCCESS; > +} > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH edk2-platforms v2 2/3] Silicon/NXP: LS1043A: Add SerDes Support 2020-06-07 13:15 [PATCH edk2-platforms v2 0/3] Add SerDes Support Wasim Khan 2020-06-07 13:15 ` [PATCH edk2-platforms v2 1/3] Silicon/NXP/Library: Implement SerDesHelperLib Wasim Khan @ 2020-06-07 13:15 ` Wasim Khan 2020-06-08 15:30 ` Leif Lindholm 2020-06-07 13:15 ` [PATCH edk2-platforms v2 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers Wasim Khan 2 siblings, 1 reply; 8+ messages in thread From: Wasim Khan @ 2020-06-07 13:15 UTC (permalink / raw) To: devel, meenakshi.aggarwal, V.Sethi, ard.biesheuvel, leif; +Cc: Wasim Khan From: Wasim Khan <wasim.khan@nxp.com> Based on SerDes protocol value in reset configuration word (RCW) different IP blocks gets enabled in HW. Add SoC specific SerDes configuration for LS1043A, which can be used by different IPs to know the enabled interfaces and perform the required initialization. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> --- Notes: Changes in V2: - Addressed review comments for structure, variable and function names - Removed SocSerDes.h and moved data definitions to SerDes.c Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 + Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf | 6 + Silicon/NXP/Include/Library/SerDes.h | 28 +++++ Silicon/NXP/LS1043A/Library/SocLib/SerDes.c | 132 ++++++++++++++++++++ 4 files changed, 168 insertions(+) diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc index e023bfbc7c04..1ac7c6da7092 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -12,6 +12,7 @@ [LibraryClasses.common] SocLib|Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf + SerDesHelperLib|Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf ################################################################################ # @@ -37,4 +38,5 @@ [PcdsFixedAtBuild.common] gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000 gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes|0x4 ## diff --git a/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf index 3d0f988e1c67..728e8f0c8ee1 100644 --- a/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf +++ b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf @@ -22,6 +22,12 @@ [Packages] [LibraryClasses] ChassisLib DebugLib + PcdLib + SerDesHelperLib [Sources.common] + SerDes.c SocLib.c + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes diff --git a/Silicon/NXP/Include/Library/SerDes.h b/Silicon/NXP/Include/Library/SerDes.h new file mode 100644 index 000000000000..f015b40403c5 --- /dev/null +++ b/Silicon/NXP/Include/Library/SerDes.h @@ -0,0 +1,28 @@ +/** SerDes.h + Header file for SoC specific SerDes routines + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef SERDES_H +#define SERDES_H + +VOID +GetSerDesProtocolMap ( + OUT UINT64 *SerDesProtocolMap + ); + +typedef VOID +(*SERDES_PROBE_LANES_CALLBACK) ( + IN UINT32 LaneProtocol, + IN VOID *Arg + ); + +VOID +SerDesProbeLanes ( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ); +#endif diff --git a/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c b/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c new file mode 100644 index 000000000000..90fa7146faa7 --- /dev/null +++ b/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c @@ -0,0 +1,132 @@ +/** SerDes.c + Provides SoC specific SerDes interface + + Copyright 2017-2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Library/ChassisLib.h> +#include <Library/DebugLib.h> +#include <Library/SerDesHelperLib.h> +#include <Soc.h> +#include <Uefi.h> + +// SerDes1 Protocol Mask in Reset Configuration Word (RCW) Status Register +#define SERDES1_PROTOCOL_MASK 0xffff0000 + +// SerDes1 Protocol Shift in Reset Configuration Word (RCW) Status Register +#define SERDES1_PROTOCOL_SHIFT 16 + +typedef enum { + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + SATA, + SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, + QSGMII_FM1_A, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SERDES_PROTOCOL_COUNT +} SERDES_PROTOCOL; + +SERDES_CONFIG gSerDes1ConfigTable[] = { + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } }, + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } }, + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } }, + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } }, + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } }, + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } }, + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } }, + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } }, + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } }, + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } }, + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, + {} +}; + +SERDES_CONFIG *gSerDesConfig[] = { + gSerDes1ConfigTable +}; + +/** + Probe all SerDes for lane protocol and execute provided callback function. + + @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol + @param Arg Pointer to Arguments to be passed to callback function. + +**/ +VOID +SerDesProbeLanes ( + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, + IN VOID *Arg + ) +{ + UINT32 SerDesProtocol; + LS1043A_DEVICE_CONFIG *DeviceConfig; + + DeviceConfig = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; + SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1_PROTOCOL_MASK; + SerDesProtocol >>= SERDES1_PROTOCOL_SHIFT; + + SerDesInstanceProbeLanes (SERDES_1, SerDesProtocol, + FixedPcdGet8 (PcdSerDesLanes), + SERDES_PROTOCOL_COUNT, + gSerDesConfig[SERDES_1], + SerDesLaneProbeCallback, + Arg); +} + +/** + Function to return SerDes protocol map for all SerDes available on board. + + @param SerDesProtocolMap Pointer to SerDes protocl map. + +**/ +VOID +GetSerDesProtocolMap ( + OUT UINT64 *SerDesProtocolMap + ) +{ + UINT32 SerDesProtocol; + LS1043A_DEVICE_CONFIG *DeviceConfig; + EFI_STATUS Status; + + *SerDesProtocolMap = 0; + DeviceConfig = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; + SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1_PROTOCOL_MASK; + SerDesProtocol >>= SERDES1_PROTOCOL_SHIFT; + + Status = GetSerDesMap (SERDES_1, SerDesProtocol, FixedPcdGet8 (PcdSerDesLanes), + SERDES_PROTOCOL_COUNT, gSerDesConfig[SERDES_1], + SerDesProtocolMap); + + if (Status != EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "%a: failed for SerDes1 \n",__FUNCTION__)); + *SerDesProtocolMap = 0; + } +} -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH edk2-platforms v2 2/3] Silicon/NXP: LS1043A: Add SerDes Support 2020-06-07 13:15 ` [PATCH edk2-platforms v2 2/3] Silicon/NXP: LS1043A: Add SerDes Support Wasim Khan @ 2020-06-08 15:30 ` Leif Lindholm 2020-06-08 16:50 ` Wasim Khan (OSS) 0 siblings, 1 reply; 8+ messages in thread From: Leif Lindholm @ 2020-06-08 15:30 UTC (permalink / raw) To: Wasim Khan; +Cc: devel, meenakshi.aggarwal, V.Sethi, ard.biesheuvel, Wasim Khan On Sun, Jun 07, 2020 at 18:45:49 +0530, Wasim Khan wrote: > From: Wasim Khan <wasim.khan@nxp.com> > > Based on SerDes protocol value in reset configuration word (RCW) > different IP blocks gets enabled in HW. > Add SoC specific SerDes configuration for LS1043A, which can be > used by different IPs to know the enabled interfaces and perform > the required initialization. > > Signed-off-by: Wasim Khan <wasim.khan@nxp.com> > --- > > Notes: > Changes in V2: > - Addressed review comments for structure, variable and function names > - Removed SocSerDes.h and moved data definitions to SerDes.c > > Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 + > Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf | 6 + > Silicon/NXP/Include/Library/SerDes.h | 28 +++++ > Silicon/NXP/LS1043A/Library/SocLib/SerDes.c | 132 ++++++++++++++++++++ > 4 files changed, 168 insertions(+) > > diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc > index e023bfbc7c04..1ac7c6da7092 100644 > --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc > +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc > @@ -12,6 +12,7 @@ > [LibraryClasses.common] > SocLib|Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf > SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf > + SerDesHelperLib|Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib.inf > > ################################################################################ > # > @@ -37,4 +38,5 @@ [PcdsFixedAtBuild.common] > gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3 > gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000 > gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC > + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes|0x4 > ## > diff --git a/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf > index 3d0f988e1c67..728e8f0c8ee1 100644 > --- a/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf > +++ b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf > @@ -22,6 +22,12 @@ [Packages] > [LibraryClasses] > ChassisLib > DebugLib > + PcdLib > + SerDesHelperLib > > [Sources.common] > + SerDes.c > SocLib.c > + > +[FixedPcd] > + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes > diff --git a/Silicon/NXP/Include/Library/SerDes.h b/Silicon/NXP/Include/Library/SerDes.h > new file mode 100644 > index 000000000000..f015b40403c5 > --- /dev/null > +++ b/Silicon/NXP/Include/Library/SerDes.h > @@ -0,0 +1,28 @@ > +/** SerDes.h > + Header file for SoC specific SerDes routines > + > + Copyright 2017-2020 NXP > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef SERDES_H > +#define SERDES_H > + > +VOID > +GetSerDesProtocolMap ( > + OUT UINT64 *SerDesProtocolMap > + ); > + > +typedef VOID > +(*SERDES_PROBE_LANES_CALLBACK) ( > + IN UINT32 LaneProtocol, > + IN VOID *Arg > + ); > + > +VOID > +SerDesProbeLanes ( > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > + IN VOID *Arg > + ); > +#endif > diff --git a/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c b/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c > new file mode 100644 > index 000000000000..90fa7146faa7 > --- /dev/null > +++ b/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c > @@ -0,0 +1,132 @@ > +/** SerDes.c > + Provides SoC specific SerDes interface > + > + Copyright 2017-2020 NXP > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include <Library/ChassisLib.h> > +#include <Library/DebugLib.h> > +#include <Library/SerDesHelperLib.h> > +#include <Soc.h> > +#include <Uefi.h> > + > +// SerDes1 Protocol Mask in Reset Configuration Word (RCW) Status Register > +#define SERDES1_PROTOCOL_MASK 0xffff0000 > + > +// SerDes1 Protocol Shift in Reset Configuration Word (RCW) Status Register > +#define SERDES1_PROTOCOL_SHIFT 16 > + > +typedef enum { > + NONE = 0, > + PCIE1, > + PCIE2, > + PCIE3, > + SATA, > + SGMII_FM1_DTSEC1, > + SGMII_FM1_DTSEC2, > + SGMII_FM1_DTSEC5, > + SGMII_FM1_DTSEC6, > + SGMII_FM1_DTSEC9, > + SGMII_FM1_DTSEC10, > + QSGMII_FM1_A, > + XFI_FM1_MAC9, > + XFI_FM1_MAC10, > + SGMII_2500_FM1_DTSEC2, > + SGMII_2500_FM1_DTSEC5, > + SGMII_2500_FM1_DTSEC9, > + SGMII_2500_FM1_DTSEC10, > + SERDES_PROTOCOL_COUNT > +} SERDES_PROTOCOL; Thanks for moving the static structs over here. The typedef was fine in the .h though - are you not going to need it there at some point? > + > +SERDES_CONFIG gSerDes1ConfigTable[] = { > + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } }, > + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, > + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } }, > + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } }, > + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, > + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, > + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } }, > + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, > + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } }, > + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, > + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } }, > + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } }, > + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } }, > + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } }, > + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, > + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, > + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } }, > + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, > + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, > + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, > + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, > + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } }, > + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {} > +}; > + > +SERDES_CONFIG *gSerDesConfig[] = { > + gSerDes1ConfigTable > +}; > + > +/** > + Probe all SerDes for lane protocol and execute provided callback function. > + > + @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol > + @param Arg Pointer to Arguments to be passed to callback function. > + > +**/ > +VOID > +SerDesProbeLanes ( > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > + IN VOID *Arg > + ) > +{ > + UINT32 SerDesProtocol; > + LS1043A_DEVICE_CONFIG *DeviceConfig; > + > + DeviceConfig = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; > + SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1_PROTOCOL_MASK; > + SerDesProtocol >>= SERDES1_PROTOCOL_SHIFT; > + > + SerDesInstanceProbeLanes (SERDES_1, SerDesProtocol, > + FixedPcdGet8 (PcdSerDesLanes), > + SERDES_PROTOCOL_COUNT, > + gSerDesConfig[SERDES_1], > + SerDesLaneProbeCallback, > + Arg); And this indentation is a bit funky. > +} > + > +/** > + Function to return SerDes protocol map for all SerDes available on board. > + > + @param SerDesProtocolMap Pointer to SerDes protocl map. > + > +**/ > +VOID > +GetSerDesProtocolMap ( > + OUT UINT64 *SerDesProtocolMap > + ) > +{ > + UINT32 SerDesProtocol; > + LS1043A_DEVICE_CONFIG *DeviceConfig; > + EFI_STATUS Status; > + > + *SerDesProtocolMap = 0; > + DeviceConfig = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; > + SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & SERDES1_PROTOCOL_MASK; > + SerDesProtocol >>= SERDES1_PROTOCOL_SHIFT; > + > + Status = GetSerDesMap (SERDES_1, SerDesProtocol, FixedPcdGet8 (PcdSerDesLanes), > + SERDES_PROTOCOL_COUNT, gSerDesConfig[SERDES_1], > + SerDesProtocolMap); As is this one, in a different way to the one above. / Leif > + > + if (Status != EFI_SUCCESS) { > + DEBUG ((DEBUG_ERROR, "%a: failed for SerDes1 \n",__FUNCTION__)); > + *SerDesProtocolMap = 0; > + } > +} > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH edk2-platforms v2 2/3] Silicon/NXP: LS1043A: Add SerDes Support 2020-06-08 15:30 ` Leif Lindholm @ 2020-06-08 16:50 ` Wasim Khan (OSS) 0 siblings, 0 replies; 8+ messages in thread From: Wasim Khan (OSS) @ 2020-06-08 16:50 UTC (permalink / raw) To: Leif Lindholm, Wasim Khan (OSS) Cc: devel@edk2.groups.io, Meenakshi Aggarwal, Varun Sethi, ard.biesheuvel@arm.com > -----Original Message----- > From: Leif Lindholm <leif@nuviainc.com> > Sent: Monday, June 8, 2020 9:00 PM > To: Wasim Khan (OSS) <wasim.khan@oss.nxp.com> > Cc: devel@edk2.groups.io; Meenakshi Aggarwal > <meenakshi.aggarwal@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; > ard.biesheuvel@arm.com; Wasim Khan <wasim.khan@nxp.com> > Subject: Re: [PATCH edk2-platforms v2 2/3] Silicon/NXP: LS1043A: Add SerDes > Support > > On Sun, Jun 07, 2020 at 18:45:49 +0530, Wasim Khan wrote: > > From: Wasim Khan <wasim.khan@nxp.com> > > > > Based on SerDes protocol value in reset configuration word (RCW) > > different IP blocks gets enabled in HW. > > Add SoC specific SerDes configuration for LS1043A, which can be used > > by different IPs to know the enabled interfaces and perform the > > required initialization. > > > > Signed-off-by: Wasim Khan <wasim.khan@nxp.com> > > --- > > > > Notes: > > Changes in V2: > > - Addressed review comments for structure, variable and function names > > - Removed SocSerDes.h and moved data definitions to SerDes.c > > > > Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 + > > Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf | 6 + > > Silicon/NXP/Include/Library/SerDes.h | 28 +++++ > > Silicon/NXP/LS1043A/Library/SocLib/SerDes.c | 132 ++++++++++++++++++++ > > 4 files changed, 168 insertions(+) > > > > diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc > > b/Silicon/NXP/LS1043A/LS1043A.dsc.inc > > index e023bfbc7c04..1ac7c6da7092 100644 > > --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc > > +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc > > @@ -12,6 +12,7 @@ > > [LibraryClasses.common] > > SocLib|Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf > > SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf > > + > > + SerDesHelperLib|Silicon/NXP/Library/SerDesHelperLib/SerDesHelperLib. > > + inf > > > > > > > ################################################################# > ##### > > ########## > > # > > @@ -37,4 +38,5 @@ [PcdsFixedAtBuild.common] > > gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3 > > gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000 > > gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC > > + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes|0x4 > > ## > > diff --git a/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf > > b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf > > index 3d0f988e1c67..728e8f0c8ee1 100644 > > --- a/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf > > +++ b/Silicon/NXP/LS1043A/Library/SocLib/SocLib.inf > > @@ -22,6 +22,12 @@ [Packages] > > [LibraryClasses] > > ChassisLib > > DebugLib > > + PcdLib > > + SerDesHelperLib > > > > [Sources.common] > > + SerDes.c > > SocLib.c > > + > > +[FixedPcd] > > + gNxpQoriqLsTokenSpaceGuid.PcdSerDesLanes > > diff --git a/Silicon/NXP/Include/Library/SerDes.h > > b/Silicon/NXP/Include/Library/SerDes.h > > new file mode 100644 > > index 000000000000..f015b40403c5 > > --- /dev/null > > +++ b/Silicon/NXP/Include/Library/SerDes.h > > @@ -0,0 +1,28 @@ > > +/** SerDes.h > > + Header file for SoC specific SerDes routines > > + > > + Copyright 2017-2020 NXP > > + > > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > > + > > +#ifndef SERDES_H > > +#define SERDES_H > > + > > +VOID > > +GetSerDesProtocolMap ( > > + OUT UINT64 *SerDesProtocolMap > > + ); > > + > > +typedef VOID > > +(*SERDES_PROBE_LANES_CALLBACK) ( > > + IN UINT32 LaneProtocol, > > + IN VOID *Arg > > + ); > > + > > +VOID > > +SerDesProbeLanes ( > > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > > + IN VOID *Arg > > + ); > > +#endif > > diff --git a/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c > > b/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c > > new file mode 100644 > > index 000000000000..90fa7146faa7 > > --- /dev/null > > +++ b/Silicon/NXP/LS1043A/Library/SocLib/SerDes.c > > @@ -0,0 +1,132 @@ > > +/** SerDes.c > > + Provides SoC specific SerDes interface > > + > > + Copyright 2017-2020 NXP > > + > > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > > + > > +#include <Library/ChassisLib.h> > > +#include <Library/DebugLib.h> > > +#include <Library/SerDesHelperLib.h> > > +#include <Soc.h> > > +#include <Uefi.h> > > + > > +// SerDes1 Protocol Mask in Reset Configuration Word (RCW) Status Register > > +#define SERDES1_PROTOCOL_MASK 0xffff0000 > > + > > +// SerDes1 Protocol Shift in Reset Configuration Word (RCW) Status Register > > +#define SERDES1_PROTOCOL_SHIFT 16 > > + > > +typedef enum { > > + NONE = 0, > > + PCIE1, > > + PCIE2, > > + PCIE3, > > + SATA, > > + SGMII_FM1_DTSEC1, > > + SGMII_FM1_DTSEC2, > > + SGMII_FM1_DTSEC5, > > + SGMII_FM1_DTSEC6, > > + SGMII_FM1_DTSEC9, > > + SGMII_FM1_DTSEC10, > > + QSGMII_FM1_A, > > + XFI_FM1_MAC9, > > + XFI_FM1_MAC10, > > + SGMII_2500_FM1_DTSEC2, > > + SGMII_2500_FM1_DTSEC5, > > + SGMII_2500_FM1_DTSEC9, > > + SGMII_2500_FM1_DTSEC10, > > + SERDES_PROTOCOL_COUNT > > +} SERDES_PROTOCOL; > > Thanks for moving the static structs over here. > The typedef was fine in the .h though - are you not going to need it there at > some point? Yes, we may need it later . Thanks for catching this. > > > + > > +SERDES_CONFIG gSerDes1ConfigTable[] = { > > + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } }, > > + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, > > + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } }, > > + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } }, > > + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, > > + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } > > +}, > > + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, > > +PCIE3 } }, > > + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, > > + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } }, > > + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, > > + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } }, > > + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } }, > > + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } }, > > + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } }, > > + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, > > + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, > > + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, > > +PCIE3 } }, > > + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, > > +SGMII_FM1_DTSEC6 } }, > > + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, > > + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, > > + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, > > + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, > > + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } }, > > + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, > > +SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > > + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, > > +SGMII_FM1_DTSEC6 } }, > > + {} > > +}; > > + > > +SERDES_CONFIG *gSerDesConfig[] = { > > + gSerDes1ConfigTable > > +}; > > + > > +/** > > + Probe all SerDes for lane protocol and execute provided callback function. > > + > > + @param SerDesLaneProbeCallback Pointer Callback function to be called > for Lane protocol > > + @param Arg Pointer to Arguments to be passed to callback > function. > > + > > +**/ > > +VOID > > +SerDesProbeLanes ( > > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > > + IN VOID *Arg > > + ) > > +{ > > + UINT32 SerDesProtocol; > > + LS1043A_DEVICE_CONFIG *DeviceConfig; > > + > > + DeviceConfig = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; > > + SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & > > + SERDES1_PROTOCOL_MASK; SerDesProtocol >>= > SERDES1_PROTOCOL_SHIFT; > > + > > + SerDesInstanceProbeLanes (SERDES_1, SerDesProtocol, > > + FixedPcdGet8 (PcdSerDesLanes), > > + SERDES_PROTOCOL_COUNT, > > + gSerDesConfig[SERDES_1], > > + SerDesLaneProbeCallback, > > + Arg); > > And this indentation is a bit funky. > > > +} > > + > > +/** > > + Function to return SerDes protocol map for all SerDes available on board. > > + > > + @param SerDesProtocolMap Pointer to SerDes protocl map. > > + > > +**/ > > +VOID > > +GetSerDesProtocolMap ( > > + OUT UINT64 *SerDesProtocolMap > > + ) > > +{ > > + UINT32 SerDesProtocol; > > + LS1043A_DEVICE_CONFIG *DeviceConfig; > > + EFI_STATUS Status; > > + > > + *SerDesProtocolMap = 0; > > + DeviceConfig = (LS1043A_DEVICE_CONFIG *)LS1043A_DCFG_ADDRESS; > > + SerDesProtocol = DcfgRead32 ((UINTN)&DeviceConfig->RcwSr[4]) & > > + SERDES1_PROTOCOL_MASK; SerDesProtocol >>= > SERDES1_PROTOCOL_SHIFT; > > + > > + Status = GetSerDesMap (SERDES_1, SerDesProtocol, FixedPcdGet8 > (PcdSerDesLanes), > > + SERDES_PROTOCOL_COUNT, gSerDesConfig[SERDES_1], > > + SerDesProtocolMap); > > As is this one, in a different way to the one above. > > / > Leif > > > + > > + if (Status != EFI_SUCCESS) { > > + DEBUG ((DEBUG_ERROR, "%a: failed for SerDes1 \n",__FUNCTION__)); > > + *SerDesProtocolMap = 0; > > + } > > +} > > -- > > 2.7.4 > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH edk2-platforms v2 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers 2020-06-07 13:15 [PATCH edk2-platforms v2 0/3] Add SerDes Support Wasim Khan 2020-06-07 13:15 ` [PATCH edk2-platforms v2 1/3] Silicon/NXP/Library: Implement SerDesHelperLib Wasim Khan 2020-06-07 13:15 ` [PATCH edk2-platforms v2 2/3] Silicon/NXP: LS1043A: Add SerDes Support Wasim Khan @ 2020-06-07 13:15 ` Wasim Khan 2020-06-08 15:32 ` Leif Lindholm 2 siblings, 1 reply; 8+ messages in thread From: Wasim Khan @ 2020-06-07 13:15 UTC (permalink / raw) To: devel, meenakshi.aggarwal, V.Sethi, ard.biesheuvel, leif; +Cc: Wasim Khan From: Wasim Khan <wasim.khan@nxp.com> Based on the serdes protocol value in reset configuration word (RCW), different PCIe controllers are enabled. Get SerDes protocol map and initialize only enabled PCIe controllers. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> --- Notes: Changes in V2: - Addressed review comments for structure, variable and function names - Using BIT0 instead of 0x1u Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 + Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 +++++++++++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf index aa5a9dec7c34..6003da708698 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -28,6 +28,7 @@ [LibraryClasses] IoAccessLib MemoryAllocationLib PcdLib + SocLib [FeaturePcd] gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index e5309a4f4248..8bbbaaa6e24d 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -15,6 +15,7 @@ #include <Library/MemoryAllocationLib.h> #include <Library/PcdLib.h> #include <Library/PciHostBridgeLib.h> +#include <Library/SerDes.h> #include <Pcie.h> #include <Protocol/PciHostBridgeResourceAllocation.h> #include <Protocol/PciRootBridgeIo.h> @@ -721,6 +722,32 @@ PcieSetupCntrl ( } /** + This function checks whether PCIe is enabled or not + depending upon SoC serdes protocol map + + @param PcieNum PCIe number. + + @return The PCIe number enabled in map. + @return FALSE PCIe number is disabled in map. + +**/ +STATIC +BOOLEAN +IsPcieNumEnabled( + IN UINTN PcieNum + ) +{ + UINT64 SerDesProtocolMap; + + SerDesProtocolMap = 0; + + // Reading serdes protocol map + GetSerDesProtocolMap (&SerDesProtocolMap); + + return (SerDesProtocolMap & (BIT0 << (PcieNum))) != 0; +} + +/** Return all the root bridge instances in an array. @param Count Return the count of root bridge instances. @@ -752,13 +779,19 @@ PciHostBridgeGetRootBridges ( PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx); Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); + // Check is the PCIe controller is enabled + if (IsPcieNumEnabled (Idx + 1) == 0) { + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx is disabled \n", Idx + 1, Regs[Idx])); + continue; + } + // Check PCIe Link LinkUp = PcieLinkUp(Regs[Idx], Idx); if (!LinkUp) { continue; } - DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + 1)); + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx :Passed Linkup Phase\n", Idx + 1, Regs[Idx])); // Set up PCIe Controller and ATU windows PcieSetupCntrl (Regs[Idx], PciPhyCfg0Addr[Idx], -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH edk2-platforms v2 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers 2020-06-07 13:15 ` [PATCH edk2-platforms v2 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers Wasim Khan @ 2020-06-08 15:32 ` Leif Lindholm 0 siblings, 0 replies; 8+ messages in thread From: Leif Lindholm @ 2020-06-08 15:32 UTC (permalink / raw) To: Wasim Khan; +Cc: devel, meenakshi.aggarwal, V.Sethi, ard.biesheuvel, Wasim Khan On Sun, Jun 07, 2020 at 18:45:50 +0530, Wasim Khan wrote: > From: Wasim Khan <wasim.khan@nxp.com> > > Based on the serdes protocol value in reset configuration > word (RCW), different PCIe controllers are enabled. > Get SerDes protocol map and initialize only enabled PCIe > controllers. > > Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> For simplicity, could you send a full v3 out please? Regards, Leif > --- > > Notes: > Changes in V2: > - Addressed review comments for structure, variable and function names > - Using BIT0 instead of 0x1u > > Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 + > Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 +++++++++++++++++++- > 2 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > index aa5a9dec7c34..6003da708698 100644 > --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > @@ -28,6 +28,7 @@ [LibraryClasses] > IoAccessLib > MemoryAllocationLib > PcdLib > + SocLib > > [FeaturePcd] > gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian > diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > index e5309a4f4248..8bbbaaa6e24d 100644 > --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -15,6 +15,7 @@ > #include <Library/MemoryAllocationLib.h> > #include <Library/PcdLib.h> > #include <Library/PciHostBridgeLib.h> > +#include <Library/SerDes.h> > #include <Pcie.h> > #include <Protocol/PciHostBridgeResourceAllocation.h> > #include <Protocol/PciRootBridgeIo.h> > @@ -721,6 +722,32 @@ PcieSetupCntrl ( > } > > /** > + This function checks whether PCIe is enabled or not > + depending upon SoC serdes protocol map > + > + @param PcieNum PCIe number. > + > + @return The PCIe number enabled in map. > + @return FALSE PCIe number is disabled in map. > + > +**/ > +STATIC > +BOOLEAN > +IsPcieNumEnabled( > + IN UINTN PcieNum > + ) > +{ > + UINT64 SerDesProtocolMap; > + > + SerDesProtocolMap = 0; > + > + // Reading serdes protocol map > + GetSerDesProtocolMap (&SerDesProtocolMap); > + > + return (SerDesProtocolMap & (BIT0 << (PcieNum))) != 0; > +} > + > +/** > Return all the root bridge instances in an array. > > @param Count Return the count of root bridge instances. > @@ -752,13 +779,19 @@ PciHostBridgeGetRootBridges ( > PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx); > Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); > > + // Check is the PCIe controller is enabled > + if (IsPcieNumEnabled (Idx + 1) == 0) { > + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx is disabled \n", Idx + 1, Regs[Idx])); > + continue; > + } > + > // Check PCIe Link > LinkUp = PcieLinkUp(Regs[Idx], Idx); > > if (!LinkUp) { > continue; > } > - DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + 1)); > + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx :Passed Linkup Phase\n", Idx + 1, Regs[Idx])); > // Set up PCIe Controller and ATU windows > PcieSetupCntrl (Regs[Idx], > PciPhyCfg0Addr[Idx], > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-06-08 16:50 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-06-07 13:15 [PATCH edk2-platforms v2 0/3] Add SerDes Support Wasim Khan 2020-06-07 13:15 ` [PATCH edk2-platforms v2 1/3] Silicon/NXP/Library: Implement SerDesHelperLib Wasim Khan 2020-06-08 15:12 ` Leif Lindholm 2020-06-07 13:15 ` [PATCH edk2-platforms v2 2/3] Silicon/NXP: LS1043A: Add SerDes Support Wasim Khan 2020-06-08 15:30 ` Leif Lindholm 2020-06-08 16:50 ` Wasim Khan (OSS) 2020-06-07 13:15 ` [PATCH edk2-platforms v2 3/3] Silicon/NXP: PciHostBridgeLib: Initialize only enabled PCIe controllers Wasim Khan 2020-06-08 15:32 ` Leif Lindholm
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