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X-MS-Exchange-AntiSpam-MessageData: Uw5ZvkvvHoSXugdgs/iHL1fMgEuVLMdiaDL930JLz95/EbMwVR+ss2QJ/2yVH93o+OwTbo2mi9o35nwELavBcmgUZMspwKO0TxXp8lZ/pC/DJO7BeEe/4xM90+XQ2J6MufGG1xjQsrrkhPbG/O2SuPoLxiImwb9DqidsOpTadmUpqbgx+gXgkoh2nymzSci8m83/AqYX10zxe8xAdx73rKQMHFOSZwwnzETAdgQx+xHCp6zmjn4vZdGfK0jHqMUpyn/QlVT4fRbTf/Rhq+pm7sVKvYGBkCZu94xRwhOmVIeSBZuBv5076MLCjsI1voMpKs3GArg/BGmHiYjlnLMl7pyMDOnDhP+5Jhe2ijcFsYB629HX/nZVKw2ncYnZ0mEReVNDmfl58G4Vl9KilOFFx2/Rh45sVF0Ax1a7SV1POvYBQPDJX2gfuAz5gCR3f3lj0x7j4ewZsqVuWdNtfc/NU/tKhU59NMthDSp5oOVGWWk= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e019f02-193f-4ce2-a319-08d80bdd2bde X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2020 18:53:02.8152 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: uZderXxN4ThE3SyEVsPyGBWJi4dLRUYNa4zkUd/vhW35EHgiEeDjt2BtE63mRcz4cbh0bOoiGHOkJ77ut38kig== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6606 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Wasim Khan Based on the serdes protocol value in reset configuration word (RCW), different PCIe controllers are enabled. Get SerDes protocol map and initialize only enabled PCIe controllers. Signed-off-by: Wasim Khan Reviewed-by: Leif Lindholm --- Notes: Changes in V5: - No Change =20 Changes in V4: - No Change =20 Changes in V3: - No Change =20 Changes in V2: - Addressed review comments for structure, variable and function names - Using BIT0 instead of 0x1u Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 1 + Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 35 +++++++++++= ++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Si= licon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf index aa5a9dec7c34..6003da708698 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -28,6 +28,7 @@ [LibraryClasses] IoAccessLib MemoryAllocationLib PcdLib + SocLib =20 [FeaturePcd] gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Sili= con/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index e5309a4f4248..8bbbaaa6e24d 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -721,6 +722,32 @@ PcieSetupCntrl ( } =20 /** + This function checks whether PCIe is enabled or not + depending upon SoC serdes protocol map + + @param PcieNum PCIe number. + + @return The PCIe number enabled in map. + @return FALSE PCIe number is disabled in map. + +**/ +STATIC +BOOLEAN +IsPcieNumEnabled( + IN UINTN PcieNum + ) +{ + UINT64 SerDesProtocolMap; + + SerDesProtocolMap =3D 0; + + // Reading serdes protocol map + GetSerDesProtocolMap (&SerDesProtocolMap); + + return (SerDesProtocolMap & (BIT0 << (PcieNum))) !=3D 0; +} + +/** Return all the root bridge instances in an array. =20 @param Count Return the count of root bridge instances. @@ -752,13 +779,19 @@ PciHostBridgeGetRootBridges ( PciPhyIoAddr [Idx] =3D PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx); Regs[Idx] =3D PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); =20 + // Check is the PCIe controller is enabled + if (IsPcieNumEnabled (Idx + 1) =3D=3D 0) { + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx is disabled \n", Idx + 1, Re= gs[Idx])); + continue; + } + // Check PCIe Link LinkUp =3D PcieLinkUp(Regs[Idx], Idx); =20 if (!LinkUp) { continue; } - DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + 1)); + DEBUG ((DEBUG_INFO, "PCIE%d reg @ 0x%lx :Passed Linkup Phase\n", Idx += 1, Regs[Idx])); // Set up PCIe Controller and ATU windows PcieSetupCntrl (Regs[Idx], PciPhyCfg0Addr[Idx], --=20 2.7.4