From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.8166.1593775151711055366 for ; Fri, 03 Jul 2020 04:19:11 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 668BB1042; Fri, 3 Jul 2020 04:19:11 -0700 (PDT) Received: from usa.arm.com (a074742-lin.blr.arm.com [10.162.17.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3FF473F68F; Fri, 3 Jul 2020 04:19:10 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm Subject: [edk2-platforms][PATCH v3 3/4] Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library Date: Fri, 3 Jul 2020 16:48:55 +0530 Message-Id: <1593775136-17859-4-git-send-email-pranav.madhu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593775136-17859-1-git-send-email-pranav.madhu@arm.com> References: <1593775136-17859-1-git-send-email-pranav.madhu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Deepak Pandey Neoverse N1 SoC includes a PCIe root complex to which a AHCI, GbE and USB controllers are attached as an endpoint. So implement the PciHostBridgeLib glue layer and enable support for PCIe controller and all the devices connected over the PCIe bus. Cc: Ard Biesheuvel Cc: Leif Lindholm Signed-off-by: Pranav Madhu --- Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec = | 19 ++ Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf = | 49 +++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf = | 11 ++ Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c = | 187 ++++++++++++++++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c = | 28 ++- 5 files changed, 293 insertions(+), 1 deletion(-) diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec b/Silico= n/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec index dba49e6489c0..da2443fcc52f 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec @@ -23,5 +23,24 @@ [Guids.common] gArmNeoverseN1SocTokenSpaceGuid =3D { 0xab93eb78, 0x60d7, 0x4099, { 0x= ac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } =20 [PcdsFixedAtBuild] + # PCIe + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount|18|UINT32|0x00000002 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000003 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000004 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000005 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x0= 0000006 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x0000= 0007 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32= |0x00000008 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x= 00000009 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32= |0x0000000A + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size|0x04000000|UINT32|0x= 0000000B + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Translation|0x0|UINT32|0x= 0000000C + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base|0x0900000000|UINT64|= 0x0000000D + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT= 64|0x0000000E + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|= 0x0000000F + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x= 00000010 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x600= 00000|UINT32|0x00000011 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x000010= 00|UINT32|0x00000012 + # Secondary DDR memory gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBr= idgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostB= ridgeLib.inf new file mode 100644 index 000000000000..7327a4d7337e --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib= .inf @@ -0,0 +1,49 @@ +## @file +# PCI Host Bridge Library instance for ARM Neoverse N1 platform. +# +# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PciHostBridgeLib + FILE_GUID =3D daa340e1-89dd-4bd2-b645-ebe75e541f8= b + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER + +[Sources] + PciHostBridgeLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1SocPlatform.dec + +[LibraryClasses] + BaseLib + DebugLib + DevicePathLib + IoLib + MemoryAllocationLib + UefiBootServicesTableLib + +[FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size + +[Protocols] + gEfiCpuIo2ProtocolGuid + +[Depex] + gEfiCpuIo2ProtocolGuid diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.in= f b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf index b2ea10756071..b8b5a5734ad6 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -29,11 +29,22 @@ [Sources.AARCH64] AArch64/Helper.S | GCC =20 [FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdArmPrimaryCore gArmTokenSpaceGuid.PcdArmPrimaryCoreMask =20 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base =20 [Guids] diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBr= idgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBri= dgeLib.c new file mode 100644 index 000000000000..4038dbf7b7fb --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib= .c @@ -0,0 +1,187 @@ +/** @file +* PCI Host Bridge Library instance for ARM Neoverse N1 platform +* +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED +STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D= { + L"Mem", L"I/O", L"Bus" +}; + +#pragma pack (1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] =3D= { + // PCIe + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCIe + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + } +}; + +STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { + { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigS= pace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttribu= tes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPcieBusMin), + FixedPcdGet32 (PcdPcieBusMax) + }, { + // Io + FixedPcdGet64 (PcdPcieIoBase), + FixedPcdGet64 (PcdPcieIoBase) + FixedPcdGet64 (PcdPcieIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPcieMmio32Base), + FixedPcdGet32 (PcdPcieMmio32Base) + FixedPcdGet32 (PcdPcieMmio32Si= ze) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPcieMmio64Base), + FixedPcdGet64 (PcdPcieMmio64Base) + FixedPcdGet64 (PcdPcieMmio64Si= ze) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] + } +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + *Count =3D ARRAY_SIZE (mPciRootBridge); + return mPciRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRoo= tBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the re= sources + for all the root bridges. The resource for eac= h root + bridge is terminated with END descriptor and a= n + additional END is appended indicating the end = of the + entire resources. The resource descriptor fiel= d + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOC= OL.\ + SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex =3D 0; + + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happened!\n")); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descri= ptor++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) + ) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResTy= pe], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag =3D %ld / %0= 2x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFl= ag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFE= TCHABLE + ) !=3D 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem= .c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index 0234748fa72e..2c2e5a67e8ec 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -13,7 +13,7 @@ #include =20 // The total number of descriptors, including the final "end-of-table" d= escriptor. -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13 =20 /** Returns the Virtual Memory Map of the platform. @@ -89,6 +89,32 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_NON_SECURE= _SRAM_SZ; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_UNCACHED_UNBUFFERED; =20 + // PCIe RC Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdPcieRootPor= tConfigBaseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdPcieRootPor= tConfigBaseAddress); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdPcieRootPor= tConfigBaseSize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + + // PCIe ECAM Configuration Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpressB= aseAddress); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciExpressB= aseAddress); + VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPcieB= usMax) - + FixedPcdGet32 (PcdPcieBus= Min) + 1) * + SIZE_1MB; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + + // PCIe MMIO32 Memory Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet32 (PcdPcieMmio32B= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet32 (PcdPcieMmio32B= ase); + VirtualMemoryTable[Index].Length =3D PcdGet32 (PcdPcieMmio32S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + + // PCIe MMIO64 Memory Space + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPcieMmio64B= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPcieMmio64B= ase); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdPcieMmio64S= ize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + // SubSystem Pheripherals - UART0 VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_UART0_BASE= ; VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_UART0_BASE= ; --=20 2.7.4