From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.13207.1595148548689488250 for ; Sun, 19 Jul 2020 01:49:09 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C7466D6E; Sun, 19 Jul 2020 01:49:07 -0700 (PDT) Received: from usa.arm.com (a074742-lin.blr.arm.com [10.162.17.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9629D3F718; Sun, 19 Jul 2020 01:49:06 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm Subject: [edk2-platforms][PATCH v4 0/5] Platform: Add initial support for N1SDP board Date: Sun, 19 Jul 2020 14:18:38 +0530 Message-Id: <1595148523-22302-1-git-send-email-pranav.madhu@arm.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Changes since v3: - Addressed all the comments from Leif. As part of the clean up that resulted from addressing the comments, some of the comments where not applicable anymore (due to fragments of code that had comments were removed during cleanup). - Included detailed description of the workarounds applied to the Neoverse N1 SoC specific PciExpressLib library. - Updated Maintainers.txt to add Silicon/ARM/ directory under ARM entry. - Picked up Leif's Reviewed-by tag for the 4th patch of this series. - Addressed all the comments from Ard. Changes since v2: - Addressed comments from Thomas. - Renamed Silicon/ARM/N1SDP to Silicon/ARM/NeoverseN1Soc. Changes since v1: - Addressed comments from Ard. - Split the code between Silicon and Platform directories. Arm's N1SDP is a Arm v8.2-A Neoverse N1 CPU based reference design platfo= rm primariliy intended for development on Arm64 based platform. This patch s= eries adds initial platform support for this board. The first patch in this series adds the platform libary implementation. T= he second patch adds a custom implementation of the PciExpressLib due to a P= CIe integration issue which results in all config space accesses to non-exist= ing BDFs resulting in a Serror (bus abort). To avoid this, the N1SDP specific PciExpressLib implementation provides a workaround for this issue. The th= ird patch in this series adds the platform library for the PciHostBridge. The fourth patch adds the initial platform support for the N1SDP platform. Th= e fifth patch adds Silicon/ARM/ to ARM entry in maintainers file. Deepak Pandey (4): Silicon/ARM/N1SoC: Add platform library implementation Silicon/ARM/N1SoC: Implement Neoverse N1 Soc specific PciExpressLib Silicon/ARM/N1SoC: Implement the PciHostBridgeLib library Platform/ARM/N1SDP: Add initial N1SDP platform support Pranav Madhu (1): Maintainers.txt: Add Silicon/ARM directory Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec = | 46 + Platform/ARM/N1Sdp/N1SdpPlatform.dsc = | 245 +++ Platform/ARM/N1Sdp/N1SdpPlatform.fdf = | 294 ++++ Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressL= ib.inf | 56 + Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf = | 49 + Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf = | 54 + Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h = | 66 + Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressL= ib.c | 1589 ++++++++++++++++++++ Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c = | 184 +++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c = | 67 + Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c = | 151 ++ Maintainers.txt = | 1 + Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S = | 84 ++ 13 files changed, 2886 insertions(+) create mode 100644 Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.dsc create mode 100644 Platform/ARM/N1Sdp/N1SdpPlatform.fdf create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExp= ressLib/PciExpressLib.inf create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/Pc= iHostBridgeLib.inf create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/Platfor= mLib.inf create mode 100644 Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExp= ressLib/PciExpressLib.c create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/Pc= iHostBridgeLib.c create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/Platfor= mLib.c create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/Platfor= mLibMem.c create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64= /Helper.S --=20 2.7.4