From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.21186.1595431549134690197 for ; Wed, 22 Jul 2020 08:25:49 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B7860D6E; Wed, 22 Jul 2020 08:25:48 -0700 (PDT) Received: from usa.arm.com (a074742-lin.blr.arm.com [10.162.17.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 589253F66E; Wed, 22 Jul 2020 08:25:47 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm Subject: [edk2-platforms][PATCH v5 1/5] Silicon/ARM/N1SoC: Add platform library implementation Date: Wed, 22 Jul 2020 20:55:20 +0530 Message-Id: <1595431524-13782-2-git-send-email-pranav.madhu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595431524-13782-1-git-send-email-pranav.madhu@arm.com> References: <1595431524-13782-1-git-send-email-pranav.madhu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Deepak Pandey Add the initial Arm's Neoverse N1 System-on-Chip platform library support. This includes the virtual memory map and helper functions for platform initialization. Cc: Ard Biesheuvel Cc: Leif Lindholm Signed-off-by: Pranav Madhu --- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 27 +++= ++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf | 43 +++= ++++ Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 66 +++= ++++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c | 67 +++= ++++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 125 +++= +++++++++++++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S | 84 +++= ++++++++++ 6 files changed, 412 insertions(+) diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/Ne= overseN1Soc/NeoverseN1Soc.dec new file mode 100644 index 000000000000..dba49e6489c0 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec @@ -0,0 +1,27 @@ +# +# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + PACKAGE_NAME =3D NeoverseN1Soc + PACKAGE_GUID =3D b6d2d197-76d0-401f-a3e0-826a26f350c= 9 + PACKAGE_VERSION =3D 0.1 + +########################################################################= ######## +# +# Include Section - list of Include Paths that are provided by this pack= age. +# Comments are used for Keywords and Module Types. +# +########################################################################= ######## +[Includes.common] + Include # Root include for the package + +[Guids.common] + gArmNeoverseN1SocTokenSpaceGuid =3D { 0xab93eb78, 0x60d7, 0x4099, { 0x= ac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } + +[PcdsFixedAtBuild] + # Secondary DDR memory + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.in= f b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 000000000000..e4d720bd36f5 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,43 @@ +## @file +# +# Copyright (c) 2018-2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D ArmNeoverseN1SocLib + FILE_GUID =3D 3d0eafcf-abc1-43d8-9269-709bb24f9d2= 1 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec + +[Sources.common] + PlatformLibMem.c + PlatformLib.c + +[Sources.AARCH64] + AArch64/Helper.S | GCC + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base + +[Guids] + gEfiHobListGuid ## CONSUMES ## SystemTable + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/= ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h new file mode 100644 index 000000000000..52e7f92e833a --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h @@ -0,0 +1,66 @@ +/** @file +* +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef NEOVERSEN1SOC_PLATFORM_H_ +#define NEOVERSEN1SOC_PLATFORM_H_ + +#define NEOVERSEN1SOC_DRAM_BLOCK1_SIZE SIZE_2GB + +//**********************************************************************= ******** +// Platform Memory Map +//**********************************************************************= ******** + +// SubSystem Peripherals - UART0 +#define NEOVERSEN1SOC_UART0_BASE 0x2A400000 +#define NEOVERSEN1SOC_UART0_SZ SIZE_64KB + +// SubSystem Peripherals - UART1 +#define NEOVERSEN1SOC_UART1_BASE 0x2A410000 +#define NEOVERSEN1SOC_UART1_SZ SIZE_64KB + +// SubSystem Peripherals - Generic Watchdog +#define NEOVERSEN1SOC_GENERIC_WDOG_BASE 0x2A440000 +#define NEOVERSEN1SOC_GENERIC_WDOG_SZ SIZE_128KB + +// SubSystem Peripherals - GIC(600) +#define NEOVERSEN1SOC_GIC_BASE 0x30000000 +#define NEOVERSEN1SOC_GICR_BASE 0x300C0000 +#define NEOVERSEN1SOC_GIC_SZ SIZE_256KB +#define NEOVERSEN1SOC_GICR_SZ SIZE_1MB + +// SubSystem non-secure SRAM +#define NEOVERSEN1SOC_NON_SECURE_SRAM_BASE 0x06000000 +#define NEOVERSEN1SOC_NON_SECURE_SRAM_SZ SIZE_64KB + +// AXI Expansion peripherals +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 +#define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 + +// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is +// pre-populated by a earlier boot stage +#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_= SECURE_SRAM_BASE + \ + 0x00008000) + +/* + * Platform information structure stored in non-secure SRAM. Platform + * information are passed from the trusted firmware with the below struc= ture + * format. The elements of NEOVERSEN1SOC_PLAT_INFO should be always in s= ync + * with the lower level firmware. + */ +typedef struct { + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + UINT8 MultichipMode; + /*! Slave count in C2C mode */ + UINT8 SlaveCount; + /*! Local DDR memory size in GigaBytes */ + UINT8 LocalDdrSize; + /*! Remote DDR memory size in GigaBytes */ + UINT8 RemoteDdrSize; +} NEOVERSEN1SOC_PLAT_INFO; + +#endif diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c = b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c new file mode 100644 index 000000000000..f722080e566b --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c @@ -0,0 +1,67 @@ +/** @file +* +* Copyright (c) 2018-2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include + +STATIC ARM_CORE_INFO mCoreInfoTable[] =3D { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 + { 0x1, 0x0 }, // Cluster 1, Core 0 + { 0x1, 0x1 } // Cluster 1, Core 1 +}; + +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof (mCoreInfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable =3D mCoreInfoTable; + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { + PrePeiCoreGetMpCoreInfo +}; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof (gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem= .c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c new file mode 100644 index 000000000000..096832be96da --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -0,0 +1,125 @@ +/** @file +* +* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include + +// The total number of descriptors, including the final "end-of-table" d= escriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 + +/** + Returns the Virtual Memory Map of the platform. + + This Virtual Memory Map is used by MemoryInitPei Module to initialize = the MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR des= cribing + a Physical-to-Virtual Memory mapping. Thi= s array + must be ended by a zero-filled entry. +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap + ) +{ + UINTN Index =3D 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT64 DramBlock2Size; + + PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT= _BASE; + DramBlock2Size =3D ((UINT64)(PlatInfo->LocalDdrSize - + NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) = * + (UINT64)SIZE_1GB); + + ResourceAttributes =3D + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdDramBlock2Base), + DramBlock2Size); + + ASSERT (VirtualMemoryMap !=3D NULL); + Index =3D 0; + + VirtualMemoryTable =3D AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIP= TOR) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)= ; + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + // SubSystem Peripherals - Generic Watchdog + VirtualMemoryTable[Index].PhysicalBase =3D NEOVERSEN1SOC_GENERIC_WD= OG_BASE; + VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_GENERIC_WD= OG_BASE; + VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_GENERIC_WD= OG_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + + // SubSystem Peripherals - GIC-600 + VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_GIC_BASE; + VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_GIC_BASE; + VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_GIC_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + + // SubSystem Peripherals - GICR-600 + VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_GICR_BASE; + VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_GICR_BASE; + VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_GICR_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + + // OnChip non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_NON_SECURE= _SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_NON_SECURE= _SRAM_BASE; + VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_NON_SECURE= _SRAM_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_UNCACHED_UNBUFFERED; + + // SubSystem Pheripherals - UART0 + VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_UART0_BASE= ; + VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_UART0_BASE= ; + VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_UART0_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + + // DDR Primary (2GB) + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemor= yBase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemor= yBase); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemor= ySize); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_WRITE_BACK; + + // DDR Secondary + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdDramBlock2B= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdDramBlock2B= ase); + VirtualMemoryTable[Index].Length =3D DramBlock2Size; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_WRITE_BACK; + + // Expansion Peripherals + VirtualMemoryTable[++Index].PhysicalBase =3D NEOVERSEN1SOC_EXP_PERIPH= _BASE0; + VirtualMemoryTable[Index].VirtualBase =3D NEOVERSEN1SOC_EXP_PERIPH= _BASE0; + VirtualMemoryTable[Index].Length =3D NEOVERSEN1SOC_EXP_PERIPH= _BASE0_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRI= BUTES)0; + + ASSERT((Index) < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + DEBUG ((DEBUG_INIT, "Virtual Memory Table setup complete.\n")); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper= .S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S new file mode 100644 index 000000000000..8d2069dea837 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S @@ -0,0 +1,84 @@ +/** @file +* +* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + +// +// First platform specific function to be called in the PEI phase +// +// This function is actually the first function called by the PrePi +// or PrePeiCore modules. It allows to retrieve arguments passed to +// the UEFI firmware through the CPU registers. +// +ASM_PFX(ArmPlatformPeiBootAction): + ret + +// +// Return the core position from the value of its MpId register +// +// This function returns core position from the position 0 in the proces= sor. +// This function might be called from assembler before any stack is set. +// +// @return Return the core position +// +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 2) + CoreId +ASM_PFX(ArmPlatformGetCorePosition): + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +// +// Return the MpId of the primary core +// +// This function returns the MpId of the primary core. +// This function might be called from assembler before any stack is set. +// +// @return Return the MpId of the primary core +// +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +// +// Return a non-zero value if the callee is the primary core +// +// This function returns a non-zero value if the callee is the primary c= ore. +// Primary core is the core responsible to initialize hardware and run U= EFI. +// This function might be called from assembler before any stack is set. +// +// @return Return a non-zero value if the callee is the primary core. +// +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret --=20 2.7.4