From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.21187.1595431551077143239 for ; Wed, 22 Jul 2020 08:25:51 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pranav.madhu@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C95B431B; Wed, 22 Jul 2020 08:25:50 -0700 (PDT) Received: from usa.arm.com (a074742-lin.blr.arm.com [10.162.17.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 31AB13F66E; Wed, 22 Jul 2020 08:25:48 -0700 (PDT) From: "Pranav Madhu" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm Subject: [edk2-platforms][PATCH v5 2/5] Silicon/ARM/N1SoC: Implement Neoverse N1 SoC specific PciExpressLib Date: Wed, 22 Jul 2020 20:55:21 +0530 Message-Id: <1595431524-13782-3-git-send-email-pranav.madhu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595431524-13782-1-git-send-email-pranav.madhu@arm.com> References: <1595431524-13782-1-git-send-email-pranav.madhu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Deepak Pandey A slave error is generated when host accesses the config space of non-available device or unimplemented function on a given bus. So implement a Neoverse N1 SoC specific PciExpressLib library with a workaround to return 0xffffffff for all such access. This library is inherited from MdePkg/Library/BasePciExpressLib and based on commit 9344f0921518 of that library in the tianocore/edk2 project. In addition to this, the Neoverse N1 SoC has two other limitations which affect the access to the PCIe root port: 1. ECAM space is not contiguous, root port ECAM (BDF =3D 0:0:0) is isolated from rest of the downstream hierarchy ECAM space. 2. Root port ECAM space is not capable of 8bit/16bit writes. This library includes workaround for these limitations as well. Cc: Ard Biesheuvel Cc: Leif Lindholm Signed-off-by: Pranav Madhu --- Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec = | 4 + Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressL= ib.inf | 56 + Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressL= ib.c | 1589 ++++++++++++++++++++ 3 files changed, 1649 insertions(+) diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/Ne= overseN1Soc/NeoverseN1Soc.dec index dba49e6489c0..491806b81be9 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec @@ -25,3 +25,7 @@ [Guids.common] [PcdsFixedAtBuild] # Secondary DDR memory gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000001 + + #PCIe + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress|0x600= 00000|UINT32|0x00000002 + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize|0x000010= 00|UINT32|0x00000003 diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib= /PciExpressLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciEx= pressLib/PciExpressLib.inf new file mode 100644 index 000000000000..acb6fb62197f --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExp= ressLib.inf @@ -0,0 +1,56 @@ +## @file +# Instance of PCI Express Library using the 256 MB PCI Express MMIO win= dow. +# +# PCI Express Library that uses the 256 MB PCI Express MMIO window to p= erform +# PCI Configuration cycles. Layers on top of an I/O Library instance. +# +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved. +# +# This library is inherited from MdePkg/Library/BasePciExpressLib. On +# NeoverseN1 SoC, with the unmodified version of this library, a slave = error is +# generated when host accesses the config space of a non-available devi= ce or +# unimplemented function on a given bus. In order to resolve this for +# NeoverseN1 SoC, a modified version of the MdePkg/Library/BasePciExpre= ssLib +# library is used. The modification includes a check to determine wheth= er the +# incoming PCI address can be safely accessed. +# +# In addition to this, the NeoverseN1 SoC has two other limitations whi= ch +# affect the access to the PCIe root port: +# 1. ECAM space is not contiguous, root port ECAM (BDF =3D 0:0:0) is = isolated +# from rest of the downstream hierarchy ECAM space. +# 2. Root port ECAM space is not capable of 8bit/16bit writes. +# This library includes workaround for these limitations as well. +# +# Copyright (c) 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D BasePciExpressLib + FILE_GUID =3D b378dd06-de7f-4e8c-8fb0-5126adfb34b= f + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciExpressLib + +[Sources] + PciExpressLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec + +[FixedPcd] + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize + +[LibraryClasses] + BaseLib + DebugLib + IoLib + PcdLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib= /PciExpressLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpr= essLib/PciExpressLib.c new file mode 100644 index 000000000000..bb0246b4a9e7 --- /dev/null +++ b/Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExp= ressLib.c @@ -0,0 +1,1589 @@ +/** @file + Functions in this library instance make use of MMIO functions in IoLib= to + access memory mapped PCI configuration space. + + All assertions for I/O operations are handled in MMIO functions in the= IoLib + Library. + + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ + On the NeoverseN1Soc, a slave error is generated when host accesses th= e + configuration space of non-available device or unimplemented function = on a + given bus. So this library introduces a workaround using IsBdfValid(), + to return 0xFFFFFFFF for all such access. + + In addition to this, the hardware has two other limitations which affe= ct + access to the PCIe root port: + 1. ECAM space is not contiguous, root port ECAM (BDF =3D 0:0:0) is i= solated + from rest of the downstream hierarchy ECAM space. + 2. Root port ECAM space is not capable of 8bit/16bit writes. + The description of the workarounds included for these limitations can + be found in the comments below. + + Copyright (c) 2020, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include + +#include +#include +#include +#include +#include +#include + +/** + Assert the validity of a PCI address. A valid PCI address should conta= in 1's + only in the low 28 bits. + + @param A The address to validate. + +**/ +#define ASSERT_INVALID_PCI_ADDRESS(A) \ + ASSERT (((A) & ~0xfffffff) =3D=3D 0) + +/* Root port Entry, BDF Entries Count */ +#define BDF_TABLE_ENTRY_SIZE 4 +#define BDF_TABLE_HEADER_COUNT 2 +#define BDF_TABLE_HEADER_SIZE 8 + +/* BDF table offsets for PCIe */ +#define PCIE_BDF_TABLE_OFFSET 0 + +#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F) +#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F) +#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07) +#define GET_REG_NUM(Address) ((Address) & 0xFFF) + +/** + BDF Table structure : (Header + BDF Entries) + -------------------------------------------- + [Offset 0x00] ROOT PORT ADDRESS + [Offset 0x04] BDF ENTRIES COUNT + [Offset 0x08] BDF ENTRY 0 + [Offset 0x0C] BDF ENTRY 1 + [Offset 0x10] BDF ENTRY 2 + [Offset 0x14] BDF ENTRY 3 + [Offset 0x18] BDF ENTRY 4 + ... + [Offset 0x--] BDF ENTRY N + -------------------------------------------- +**/ + +/** + Value returned for reads on configuration space of unimplemented + device functions. +**/ +STATIC UINTN mDummyConfigData =3D 0xFFFFFFFF; + +/** + Registers a PCI device so PCI configuration registers may be accessed = after + SetVirtualAddressMap(). + + Registers the PCI device specified by Address so all the PCI configura= tion + registers associated with that PCI device may be accessed after SetVir= tualAddressMap() + is called. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + + @retval RETURN_SUCCESS The PCI device was registered for run= time access. + @retval RETURN_UNSUPPORTED An attempt was made to call this func= tion + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the = PCI device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availa= ble to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciExpressRegisterForRuntimeAccess ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return RETURN_UNSUPPORTED; +} + +/** + Check if the requested PCI address can be safely accessed. + + SCP performs the initial bus scan, prepares a table of valid BDF addre= sses + and shares them through non-trusted SRAM. This function validates if t= he + requested PCI address belongs to a valid BDF by checking the table of = valid + entries. If not, this function will return false. This is a workaround= to + avoid bus fault that occurs when accessing unavailable PCI device due = to + hardware bug. + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + + @return TRUE BDF can be accessed, valid. + @return FALSE BDF should not be accessed, invalid. + +**/ +STATIC +BOOLEAN +IsBdfValid ( + IN UINTN Address + ) +{ + UINTN BdfCount; + UINTN BdfValue; + UINTN BdfEntry; + UINTN Count; + UINTN TableBase; + UINTN ConfigBase; + + ConfigBase =3D Address & ~0xFFF; + TableBase =3D NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + PCIE_BDF_TABLE_OFFS= ET; + BdfCount =3D MmioRead32 (TableBase + BDF_TABLE_ENTRY_SIZE); + BdfEntry =3D TableBase + BDF_TABLE_HEADER_SIZE; + + /* Skip the header & check remaining entry */ + for (Count =3D 0; Count < BdfCount; Count++, BdfEntry +=3D BDF_TABLE_E= NTRY_SIZE) { + BdfValue =3D MmioRead32 (BdfEntry); + if (BdfValue =3D=3D ConfigBase) { + return TRUE; + } + } + + return FALSE; +} + +/** + Get the physical address of a configuration space register. + + Implement a workaround to avoid generation of slave errors from the b= us. That + is, retrieve the PCI Express Base Address via a PCD entry, add the inc= omming + address with that base address and check whether this converted addres= s + points to a accessible BDF. If it is not accessible, return the addres= s + of a dummy location so that a read from it does not cause a slave erro= r. + + In addition to this, implement a workaround for accessing the root por= t's + configuration space. The root port configuration space is not contiguo= us + with the rest of the downstream hierarchy configuration space. So dete= rmine + whether the specified address is for the root port and use a different= base + address for it. + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + + @return Physical address of the configuration register that correspond= s to the + PCI configuration register specified by input parameter 'Addre= ss'. + +**/ +STATIC +VOID* +GetPciExpressAddress ( + IN UINTN Address + ) +{ + UINT8 Bus, Device, Function; + UINTN ConfigAddress; + + Bus =3D GET_BUS_NUM (Address); + Device =3D GET_DEV_NUM (Address); + Function =3D GET_FUNC_NUM (Address); + + if ((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function =3D=3D 0)) { + ConfigAddress =3D PcdGet32 (PcdPcieRootPortConfigBaseAddress) + Addr= ess; + } else { + ConfigAddress =3D PcdGet64 (PcdPciExpressBaseAddress) + Address; + if (!IsBdfValid(Address)) { + ConfigAddress =3D (UINTN)&mDummyConfigData; + } + } + + return (VOID *)ConfigAddress; +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Ad= dress. + This function must guarantee that all PCI read and write operations ar= e + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressRead8 ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioRead8 ((UINTN)GetPciExpressAddress (Address)); +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with = the + value specified by Value. Value is returned. This function must guaran= tee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + UINT8 Bus, Device, Function; + UINT8 Offset; + UINT32 Data; + + ASSERT_INVALID_PCI_ADDRESS (Address); + + Bus =3D GET_BUS_NUM (Address); + Device =3D GET_DEV_NUM (Address); + Function =3D GET_FUNC_NUM (Address); + + // + // 8-bit and 16-bit writes to root port config space is not supported = due to + // a hardware limitation. As a workaround, perform a read-update-write + // sequence on the whole 32-bit word of the root port config register = such + // that only the specified 8-bits of that word are updated. + // + if ((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function =3D=3D 0)) { + Offset =3D Address & 0x3; + Address &=3D 0xFFFFFFFC; + Data =3D MmioRead32 ((UINTN)GetPciExpressAddress (Address)); + Data &=3D ~(0xFF << (8 * Offset)); + Data |=3D (Value << (8 * Offset)); + MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data); + return Value; + } + + return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value); +} + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with + an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration regis= ter is + returned. This function must guarantee that all PCI read and write ope= rations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressOr8 ( + IN UINTN Address, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an = 8-bit + value. + + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a + bitwise AND between the read result and the value specified by AndData= , and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is return= ed. + This function must guarantee that all PCI read and write operations ar= e + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressAnd8 ( + IN UINTN Address, + IN UINT8 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an = 8-bit + value, followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a + bitwise AND between the read result and the value specified by AndData= , + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the = PCI + configuration register is returned. This function must guarantee that = all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressAndThenOr8 ( + IN UINTN Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAndThenOr8 ( + (UINTN)GetPciExpressAddress (Address), + AndData, + OrData + ); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit fi= eld is + specified by the StartBit and the EndBit. The value of the bit field i= s + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..7. + + @return The value of the bit field read from the PCI configuration reg= ister. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldRead8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldRead8 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit + ); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The b= it + field is specified by the StartBit and the EndBit. All other bits in t= he + destination PCI configuration register are preserved. The new value of= the + 8-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..7. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldWrite8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldWrite8 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + Value + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR= , and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration regis= ter is + returned. This function must guarantee that all PCI read and write ope= rations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit= and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldOr8 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + OrData + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a b= itwise + AND, and writes the result back to the bit field in the 8-bit register= . + + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a + bitwise AND between the read result and the value specified by AndData= , and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is return= ed. + This function must guarantee that all PCI read and write operations ar= e + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBi= t and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..7. + @param AndData The value to AND with the PCI configuration register= . + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldAnd8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAnd8 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData + ); +} + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by= a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, perfo= rms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the = PCI + configuration register is returned. This function must guarantee that = all PCI + read and write operations are serialized. Extra left bits in both AndD= ata and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBi= t and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit= and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..7. + @param AndData The value to AND with the PCI configuration register= . + @param OrData The value to OR with the result of the AND operation= . + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciExpressBitFieldAndThenOr8 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAndThenOr8 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData, + OrData + ); +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by A= ddress. + This function must guarantee that all PCI read and write operations ar= e + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressRead16 ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioRead16 ((UINTN)GetPciExpressAddress (Address)); +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with= the + value specified by Value. Value is returned. This function must guaran= tee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + UINT8 Bus, Device, Function; + UINT8 Offset; + UINT32 Data; + + ASSERT_INVALID_PCI_ADDRESS (Address); + + Bus =3D GET_BUS_NUM (Address); + Device =3D GET_DEV_NUM (Address); + Function =3D GET_FUNC_NUM (Address); + + // + // 8-bit and 16-bit writes to root port config space is not supported = due to + // a hardware limitation. As a workaround, perform a read-update-write + // sequence on the whole 32-bit word of the root port config register = such + // that only the specified 16-bits of that word are updated. + // + if ((Bus =3D=3D 0) && (Device =3D=3D 0) && (Function =3D=3D 0)) { + Offset =3D Address & 0x3; + Address &=3D 0xFFFFFFFC; + Data =3D MmioRead32 ((UINTN)GetPciExpressAddress (Address)); + Data &=3D ~(0xFFFF << (8 * Offset)); + Data |=3D (Value << (8 * Offset)); + MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Data); + return Value; + } + + return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value); +} + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, perf= orms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration regis= ter is + returned. This function must guarantee that all PCI read and write ope= rations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressOr16 ( + IN UINTN Address, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 1= 6-bit + value. + + Reads the 16-bit PCI configuration register specified by Address, perf= orms a + bitwise AND between the read result and the value specified by AndData= , and + writes the result to the 16-bit PCI configuration register specified b= y + Address. The value written to the PCI configuration register is return= ed. + This function must guarantee that all PCI read and write operations ar= e + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressAnd16 ( + IN UINTN Address, + IN UINT16 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 1= 6-bit + value, followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, perf= orms a + bitwise AND between the read result and the value specified by AndData= , + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the = PCI + configuration register is returned. This function must guarantee that = all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressAndThenOr16 ( + IN UINTN Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAndThenOr16 ( + (UINTN)GetPciExpressAddress (Address), + AndData, + OrData + ); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit fi= eld is + specified by the StartBit and the EndBit. The value of the bit field i= s + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..15. + + @return The value of the bit field read from the PCI configuration reg= ister. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldRead16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldRead16 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit + ); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The b= it + field is specified by the StartBit and the EndBit. All other bits in t= he + destination PCI configuration register are preserved. The new value of= the + 16-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..15. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldWrite16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldWrite16 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + Value + ); +} + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR= , and + writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, perf= orms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration regis= ter is + returned. This function must guarantee that all PCI read and write ope= rations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit= and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldOr16 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + OrData + ); +} + +/** + Reads a bit field in a 16-bit PCI configuration register, performs a b= itwise + AND, and writes the result back to the bit field in the 16-bit registe= r. + + Reads the 16-bit PCI configuration register specified by Address, perf= orms a + bitwise AND between the read result and the value specified by AndData= , and + writes the result to the 16-bit PCI configuration register specified b= y + Address. The value written to the PCI configuration register is return= ed. + This function must guarantee that all PCI read and write operations ar= e + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBi= t and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..15. + @param AndData The value to AND with the PCI configuration register= . + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldAnd16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAnd16 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData + ); +} + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by= a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, perf= orms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PC= I + configuration register specified by Address. The value written to the = PCI + configuration register is returned. This function must guarantee that = all PCI + read and write operations are serialized. Extra left bits in both AndD= ata and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBi= t and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit= and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..15. + @param AndData The value to AND with the PCI configuration register= . + @param OrData The value to OR with the result of the AND operation= . + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciExpressBitFieldAndThenOr16 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAndThenOr16 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData, + OrData + ); +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by A= ddress. + This function must guarantee that all PCI read and write operations ar= e + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + + @return The read value from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressRead32 ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioRead32 ((UINTN)GetPciExpressAddress (Address)); +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with= the + value specified by Value. Value is returned. This function must guaran= tee + that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value); +} + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with + a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, perf= orms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration regis= ter is + returned. This function must guarantee that all PCI read and write ope= rations + are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressOr32 ( + IN UINTN Address, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 3= 2-bit + value. + + Reads the 32-bit PCI configuration register specified by Address, perf= orms a + bitwise AND between the read result and the value specified by AndData= , and + writes the result to the 32-bit PCI configuration register specified b= y + Address. The value written to the PCI configuration register is return= ed. + This function must guarantee that all PCI read and write operations ar= e + serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 3= 2-bit + value, followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, perf= orms a + bitwise AND between the read result and the value specified by AndData= , + performs a bitwise OR between the result of the AND operation and + the value specified by OrData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the = PCI + configuration register is returned. This function must guarantee that = all PCI + read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function= and + Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioAndThenOr32 ( + (UINTN)GetPciExpressAddress (Address), + AndData, + OrData + ); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit fi= eld is + specified by the StartBit and the EndBit. The value of the bit field i= s + returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..31. + + @return The value of the bit field read from the PCI configuration reg= ister. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldRead32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldRead32 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit + ); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The b= it + field is specified by the StartBit and the EndBit. All other bits in t= he + destination PCI configuration register are preserved. The new value of= the + 32-bit register is returned. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..31. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldWrite32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldWrite32 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + Value + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR= , and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perf= orms a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration regis= ter is + returned. This function must guarantee that all PCI read and write ope= rations + are serialized. Extra left bits in OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit= and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldOr32 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + OrData + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a b= itwise + AND, and writes the result back to the bit field in the 32-bit registe= r. + + Reads the 32-bit PCI configuration register specified by Address, perf= orms a + bitwise AND between the read result and the value specified by AndData= , and + writes the result to the 32-bit PCI configuration register specified b= y + Address. The value written to the PCI configuration register is return= ed. + This function must guarantee that all PCI read and write operations ar= e + serialized. Extra left bits in AndData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBi= t and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..31. + @param AndData The value to AND with the PCI configuration register= . + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldAnd32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAnd32 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData + ); +} + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by= a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, perf= orms a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PC= I + configuration register specified by Address. The value written to the = PCI + configuration register is returned. This function must guarantee that = all PCI + read and write operations are serialized. Extra left bits in both AndD= ata and + OrData are stripped. + + If Address > 0x0FFFFFFF, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBi= t and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit= and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit = field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit f= ield. + Range 0..31. + @param AndData The value to AND with the PCI configuration register= . + @param OrData The value to OR with the result of the AND operation= . + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciExpressBitFieldAndThenOr32 ( + IN UINTN Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + ASSERT_INVALID_PCI_ADDRESS (Address); + return MmioBitFieldAndThenOr32 ( + (UINTN)GetPciExpressAddress (Address), + StartBit, + EndBit, + AndData, + OrData + ); +} + +/** + Reads a range of PCI configuration registers into a caller supplied bu= ffer. + + Reads the range of PCI configuration registers specified by StartAddre= ss and + Size into the buffer specified by Buffer. This function only allows th= e PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used = to read + from StartAdress to StartAddress + Size. Due to alignment restrictions= , 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning = and the + end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Bus, D= evice, + Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer receiving the data read. + + @return Size read data from StartAddress. + +**/ +UINTN +EFIAPI +PciExpressReadBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_ADDRESS (StartAddress); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return Size; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & 1) !=3D 0) { + // + // Read a byte if StartAddress is byte aligned + // + *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & 2) !=3D 0) { + // + // Read a word if StartAddress is word aligned + // + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (Star= tAddress)); + + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Read as many double words as possible + // + WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (Star= tAddress)); + + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Read the last remaining word if exist + // + WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (Star= tAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Read the last remaining byte if exist + // + *(volatile UINT8 *)Buffer =3D PciExpressRead8 (StartAddress); + } + + return ReturnValue; +} + +/** + Copies the data in a caller supplied buffer to a specified range of PC= I + configuration space. + + Writes the range of PCI configuration registers specified by StartAddr= ess and + Size from the buffer specified by Buffer. This function only allows th= e PCI + configuration registers from a single PCI function to be written. Size= is + returned. When possible 32-bit PCI configuration write cycles are used= to + write from StartAdress to StartAddress + Size. Due to alignment restri= ctions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beg= inning + and the end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Bus, D= evice, + Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer containing the data to w= rite. + + @return Size written to StartAddress. + +**/ +UINTN +EFIAPI +PciExpressWriteBuffer ( + IN UINTN StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_ADDRESS (StartAddress); + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return 0; + } + + ASSERT (Buffer !=3D NULL); + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & 1) !=3D 0) { + // + // Write a byte if StartAddress is byte aligned + // + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & 2) !=3D 0) { + // + // Write a word if StartAddress is word aligned + // + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Write as many double words as possible + // + PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Write the last remaining word if exist + // + PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Write the last remaining byte if exist + // + PciExpressWrite8 (StartAddress, *(UINT8*)Buffer); + } + + return ReturnValue; +} --=20 2.7.4