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From: Meenakshi Aggarwal <meenakshi.aggarwal@oss.nxp.com>
To: ard.biesheuvel@arm.com,
leif@nuviainc.com,
michael.d.kinney@intel.com,
devel@edk2.groups.io
Cc: v.sethi@nxp.com,
Meenakshi Aggarwal <meenakshi.aggarwal@oss.nxp.com>,
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Subject: [edk2-platforms v3 4/6] Silicon/NXP: Implement USB Errata Workarounds
Date: Fri, 9 Oct 2020 20:49:02 +0530
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Implement workarounds for USB errata A008997, A009007,
A009008, A009798 for chassis2
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../NXP/Chassis2/Library/ChassisLib/ChassisLib.inf | 2 +
Silicon/NXP/Chassis2/Include/Chassis.h | 4 +
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h | 23 +++
Silicon/NXP/Include/Library/ChassisLib.h | 20 +++
Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c | 165 +++++++++++++++=
++++++
5 files changed, 214 insertions(+)
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
create mode 100644 Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf b/Sil=
icon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
index f5dbd1349dc5..d64286b199c6 100644
--- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.inf
@@ -28,6 +28,8 @@ [LibraryClasses]
=20
[Sources.common]
ChassisLib.c
+ Erratum.c
=20
[FeaturePcd]
gNxpQoriqLsTokenSpaceGuid.PcdDcfgBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian
diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis=
2/Include/Chassis.h
index 6dfce425a0b0..f8fa7ed67596 100644
--- a/Silicon/NXP/Chassis2/Include/Chassis.h
+++ b/Silicon/NXP/Chassis2/Include/Chassis.h
@@ -27,6 +27,10 @@
#define SCR0_CLIENTPD_MASK 0x00000001
#define SACR_PAGESIZE_MASK 0x00010000
=20
+#define USB_PHY1_BASE_ADDRESS 0x084F0000
+#define USB_PHY2_BASE_ADDRESS 0x08500000
+#define USB_PHY3_BASE_ADDRESS 0x08510000
+
/**
The Device Configuration Unit provides general purpose configuration a=
nd
status for the device. These registers only support 32-bit accesses.
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h b/Silicon/=
NXP/Chassis2/Library/ChassisLib/Erratum.h
new file mode 100644
index 000000000000..0231ef0a283d
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.h
@@ -0,0 +1,23 @@
+/** @file
+* Header defining the Base addresses, sizes, flags etc for Erratas
+*
+* Copyright 2020 NXP
+*
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef ERRATUM_H__
+#define ERRATUM_H__
+
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
+
+#define USB_PHY_RX_OVRD_IN_HI 0x200c
+
+#endif
diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Inclu=
de/Library/ChassisLib.h
index a038d8e5ce31..ffe57a6f019d 100644
--- a/Silicon/NXP/Include/Library/ChassisLib.h
+++ b/Silicon/NXP/Include/Library/ChassisLib.h
@@ -90,4 +90,24 @@ ChassisInit (
VOID
);
=20
+VOID
+ErratumA008997 (
+ VOID
+ );
+
+VOID
+ErratumA009007 (
+ VOID
+ );
+
+VOID
+ErratumA009008 (
+ VOID
+ );
+
+VOID
+ErratumA009798 (
+ VOID
+ );
+
#endif // CHASSIS_LIB_H__
diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c b/Silicon/=
NXP/Chassis2/Library/ChassisLib/Erratum.c
new file mode 100644
index 000000000000..4f0deb24b658
--- /dev/null
+++ b/Silicon/NXP/Chassis2/Library/ChassisLib/Erratum.c
@@ -0,0 +1,165 @@
+/** @file
+ This file containa all erratas need to be applied on different SoCs.
+
+ Copyright 2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/ChassisLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include "Erratum.h"
+
+/*
+* A-008997 : USB3 LFPS peak-to-peak differential output
+* voltage adjustment settings
+* Affects : USB
+* Description: Low Frequency Periodic Signaling (LFPS)
+* peak-to-peak differential output voltage test
+* compliance fails using default transmitter settings.
+* Software is required to change the transmitter
+* signal swings to pass compliance tests.
+* Impact : LFPS peak-to-peak differential output voltage
+* compliance test fails.
+*/
+VOID
+ErratumA008997 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg =3D (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE=
_CHASSIS2_SCFG_ADDRESS;
+
+ Value =3D ScfgRead32 ((UINTN)&Scfg->Usb1Prm2Cr);
+ Value &=3D ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm2Cr, Value | (USB_PCSTXSWINGFULL << =
9));
+ Value =3D ScfgRead32 ((UINTN)&Scfg->Usb2Prm2Cr);
+ Value &=3D ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm2Cr, Value | (USB_PCSTXSWINGFULL << =
9));
+ Value =3D ScfgRead32 ((UINTN)&Scfg->Usb3Prm2Cr);
+ Value &=3D ~(0x7F << 9);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm2Cr, Value | (USB_PCSTXSWINGFULL << =
9));
+
+ return;
+}
+
+/*
+* A-009007 : USB3PHY observing intermittent failure in
+* receive compliance tests at higher jitter frequency
+* using default register values
+* Affects : USB
+* Description: Receive compliance tests may fail intermittently at
+* high jitter frequencies using default register values.
+* Impact : Receive compliance test fails at default register setting=
.
+*/
+
+VOID
+ConfigUsbLane0 (
+ IN UINTN UsbPhy
+ )
+{
+ UINTN RegAddress;
+
+ RegAddress =3D UsbPhy + USB_PHY_RX_OVRD_IN_HI;
+
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_1);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_2);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_3);
+ ArmDataMemoryBarrier ();
+ MmioWrite16 (RegAddress, USB_PHY_RX_EQ_VAL_4);
+
+ return;
+}
+
+VOID
+ErratumA009007 (
+ VOID
+ )
+{
+ UINTN UsbPhy;
+
+ UsbPhy =3D USB_PHY1_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ UsbPhy =3D USB_PHY2_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ UsbPhy =3D USB_PHY3_BASE_ADDRESS;
+ ConfigUsbLane0 (UsbPhy);
+
+ return;
+}
+
+/*
+* A-009008 : USB High Speed (HS) eye height adjustment
+* Affects : USB
+* Description: USB HS eye diagram fails with the default
+* value at many corners, particularly at a
+* high temperature (105=C2=B0C).
+* Impact : USB HS eye diagram may fail using the default value.
+*/
+VOID
+ErratumA009008 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg =3D (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE=
_CHASSIS2_SCFG_ADDRESS;
+
+ Value =3D ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
+ Value &=3D ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+ Value =3D ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
+ Value &=3D ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+ Value =3D ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
+ Value &=3D ~(0xF << 6);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value|(USB_TXVREFTUNE << 6));
+
+ return;
+}
+
+/*
+* A-009798 : USB high speed squelch threshold adjustment
+* Affects : USB
+* Description: The default setting for USB high speed
+* squelch threshold results in a threshold close
+* to or lower than 100mV. This leads to a receiver
+* compliance test failure for a 100mV threshold.
+* Impact : If the errata is not applied, only the USB high
+* speed receiver sensitivity compliance test fails,
+* however USB data continues to transfer.
+*/
+VOID
+ErratumA009798 (
+ VOID
+ )
+{
+ NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *Scfg;
+ UINT32 Value;
+
+ Scfg =3D (NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG *)NXP_LAYERSCAPE=
_CHASSIS2_SCFG_ADDRESS;
+
+ Value =3D ScfgRead32 ((UINTN)&Scfg->Usb1Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb1Prm1Cr, Value & USB_SQRXTUNE);
+ Value =3D ScfgRead32 ((UINTN)&Scfg->Usb2Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb2Prm1Cr, Value & USB_SQRXTUNE);
+ Value =3D ScfgRead32 ((UINTN)&Scfg->Usb3Prm1Cr);
+ ScfgWrite32 ((UINTN)&Scfg->Usb3Prm1Cr, Value & USB_SQRXTUNE);
+
+ return;
+}
--=20
1.9.1