From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mx.groups.io with SMTP id smtpd.web11.8024.1607432979830761779 for ; Tue, 08 Dec 2020 05:09:40 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: huawei.com, ip: 45.249.212.35, mailfrom: xiewenyi2@huawei.com) Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4Cr0r04Mykz79pT; Tue, 8 Dec 2020 21:09:04 +0800 (CST) Received: from HGH1000039998.huawei.com (10.184.68.188) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Tue, 8 Dec 2020 21:09:28 +0800 From: "wenyi,xie" To: , , CC: , Subject: [PATCH EDK2 v1 1/1] ArmPkg/ArmDisassemblerLib: fix incorrect comparison Date: Tue, 8 Dec 2020 21:07:49 +0800 Message-ID: <1607432869-13641-2-git-send-email-xiewenyi2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1607432869-13641-1-git-send-email-xiewenyi2@huawei.com> References: <1607432869-13641-1-git-send-email-xiewenyi2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.184.68.188] X-CFilter-Loop: Reflected Content-Type: text/plain As shift = (OpCode >> 5) & 0x3, shift will never be larger than 0x3, so the comparison between shift and 0x12 will always be false. The right shift type of ASR is 0x2. Cc: Leif Lindholm Cc: Ard Biesheuvel Signed-off-by: Wenyi Xie --- ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c b/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c index b4f0f8dbbfc9..d206cf4ea908 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c @@ -240,7 +240,7 @@ DisassembleArmInstruction ( if (shift_imm == 0) { shift_imm = 32; } - } else if (shift == 0x12) { + } else if (shift == 0x2) { Type = "ASR"; } else if (shift_imm == 0) { AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W)); @@ -270,7 +270,7 @@ DisassembleArmInstruction ( if (shift_imm == 0) { shift_imm = 32; } - } else if (shift == 0x12) { + } else if (shift == 0x2) { Type = "ASR"; } else if (shift_imm == 0) { AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]); -- 2.20.1.windows.1