* [edk2-platforms] [PATCH v3 1/3] Platform/ARM/SgiPkg: Add helper macros for HMAT table
2021-02-17 11:01 [edk2-platforms] [PATCH v3 0/3] Add HMAT tables for RD multi-chip platforms Vijayenthiran Subramaniam
@ 2021-02-17 11:01 ` Vijayenthiran Subramaniam
2021-02-17 11:01 ` [edk2-platforms] [PATCH v3 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2 Vijayenthiran Subramaniam
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Vijayenthiran Subramaniam @ 2021-02-17 11:01 UTC (permalink / raw)
To: sami.mujawar, devel, leif, ardb+tianocore; +Cc: thomas.abraham
Add helper macros to create Memory Proximity Domain, System Locality
Latency and Bandwidth Information, Memory Side Cache Information
structures in the HMAT table.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
---
| 113 +++++++++++++++++++-
1 file changed, 112 insertions(+), 1 deletion(-)
--git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index 8d715de173c9..e27333d21b53 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -119,4 +119,115 @@
ACPIProcessorUID, Flags, ClockDomain \
}
+//
+// HMAT related structures
+//
+// Memory Proximity Domain Attributes Structure
+// Refer Section 5.2.27.3 in ACPI Specification, Version 6.3
+#define EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT( \
+ Flags, ProximityDomainForAttachedIntiator, ProximityDomainForMemory) \
+ { \
+ EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES), \
+ { \
+ Flags, \
+ 0 \
+ }, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ ProximityDomainForAttachedIntiator, \
+ ProximityDomainForMemory, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ } \
+ }
+
+// System Locality Latency and Bandwidth Information Structure
+// Refer Section 5.2.27.4 in ACPI Specification, Version 6.3
+#define EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT( \
+ Flags, DataType, NumInitiatorProximityDomains, \
+ NumTargetProximityDomains, EntryBaseUnit) \
+ { \
+ EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO) + \
+ (4 * NumInitiatorProximityDomains) + (4 * NumTargetProximityDomains) + \
+ (2 * NumInitiatorProximityDomains * NumTargetProximityDomains), \
+ { \
+ Flags, \
+ 0 \
+ }, \
+ DataType, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ NumInitiatorProximityDomains, \
+ NumTargetProximityDomains, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ EntryBaseUnit \
+ }
+
+// Memory Side Cache Information Structure
+// Refer Section 5.2.27.5 in ACPI Specification, Version 6.3
+#define EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT( \
+ MemoryProximityDomain, MemorySideCacheSize, CacheAttributes, \
+ NumberOfSmbiosHandles) \
+ { \
+ EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO) + \
+ (NumberOfSmbiosHandles * 2), \
+ MemoryProximityDomain, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ MemorySideCacheSize, \
+ CacheAttributes, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ NumberOfSmbiosHandles \
+ }
+
#endif /* __SGI_ACPI_HEADER__ */
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [edk2-platforms] [PATCH v3 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
2021-02-17 11:01 [edk2-platforms] [PATCH v3 0/3] Add HMAT tables for RD multi-chip platforms Vijayenthiran Subramaniam
2021-02-17 11:01 ` [edk2-platforms] [PATCH v3 1/3] Platform/ARM/SgiPkg: Add helper macros for HMAT table Vijayenthiran Subramaniam
@ 2021-02-17 11:01 ` Vijayenthiran Subramaniam
2021-04-07 18:37 ` [edk2-devel] " Sami Mujawar
2021-02-17 11:01 ` [edk2-platforms] [PATCH v3 3/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RD-V1-MC Vijayenthiran Subramaniam
2021-04-08 14:51 ` [edk2-devel] [edk2-platforms] [PATCH v3 0/3] Add HMAT tables for RD multi-chip platforms Sami Mujawar
3 siblings, 1 reply; 7+ messages in thread
From: Vijayenthiran Subramaniam @ 2021-02-17 11:01 UTC (permalink / raw)
To: sami.mujawar, devel, leif, ardb+tianocore; +Cc: thomas.abraham
Add HMAT table support for RD-N1-Edge dual-chip platform. The latencies
mentioned in the table are hypothetical values and represents typical
latency between two chips. These values are applicable only for
RD-N1-Edge dual-chip fixed virtual and should not be reused for other
platforms.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 121 ++++++++++++++++++++
2 files changed, 123 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index d44f02ab0c16..db168c518e21 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2020-2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,7 @@ [Sources]
Iort.aslc
Mcfg.aslc
RdN1Edge/Dsdt.asl
+ RdN1EdgeX2/Hmat.aslc
RdN1EdgeX2/Madt.aslc
RdN1EdgeX2/Srat.aslc
Spcr.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
new file mode 100644
index 000000000000..b1351e9305ba
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
@@ -0,0 +1,121 @@
+/** @file
+* Heterogeneous Memory Attribute Table (HMAT)
+*
+* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <SgiAcpiHeader.h>
+#include <SgiPlatform.h>
+
+#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
+#define INITATOR_PROXIMITY_DOMAIN_CNT 2
+#define TARGET_PROXIMITY_DOMAIN_CNT 2
+
+//
+// HMAT Table
+//
+#pragma pack (1)
+
+typedef struct InitiatorTargetProximityMatrix {
+ UINT32 InitatorProximityDomain[INITATOR_PROXIMITY_DOMAIN_CNT];
+ UINT32 TargetProximityDomain[TARGET_PROXIMITY_DOMAIN_CNT];
+ UINT16 MatrixEntry[INITATOR_PROXIMITY_DOMAIN_CNT * TARGET_PROXIMITY_DOMAIN_CNT];
+} INITIATOR_TARGET_PROXIMITY_MATRIX;
+
+typedef struct {
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
+ INITIATOR_TARGET_PROXIMITY_MATRIX Matrix;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
+} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
+
+#pragma pack ()
+
+#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+ ) \
+{ \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+}
+
+EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
+ // Header
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ ),
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ },
+
+ // Memory Proximity Domain
+ {
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x0, 0x0),
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x1, 0x1),
+ },
+
+ // Latency Info
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+ 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ {
+ {0, 1},
+ {0, 1},
+ {
+ //
+ // The latencies mentioned in this table are hypothetical values and
+ // represents typical latency between two chips. These values are
+ // applicable only for RD-N1-Edge dual-chip fixed virtual platform and
+ // should not be reused for other platforms.
+ //
+ 10, 20,
+ 20, 10,
+ }
+ },
+
+ // Memory Side Cache
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x0,
+ SIZE_8MB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x1,
+ SIZE_8MB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Hmat;
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [edk2-devel] [edk2-platforms] [PATCH v3 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
2021-02-17 11:01 ` [edk2-platforms] [PATCH v3 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2 Vijayenthiran Subramaniam
@ 2021-04-07 18:37 ` Sami Mujawar
2021-04-08 12:55 ` Vijayenthiran Subramaniam
0 siblings, 1 reply; 7+ messages in thread
From: Sami Mujawar @ 2021-04-07 18:37 UTC (permalink / raw)
To: Vijayenthiran Subramaniam, devel
[-- Attachment #1: Type: text/plain, Size: 513 bytes --]
Hi Vijay,
>
> +#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
> + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy,
> CacheLineSize \
> + ) \
> +{ \
> + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy,
> CacheLineSize \
> +}
This macros is again repeated in patch 3/3. I think this could be moved to Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h.
If you agree I can make this change locally before pushing this series.
Regards,
Sami Mujawar
[-- Attachment #2: Type: text/html, Size: 564 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [edk2-devel] [edk2-platforms] [PATCH v3 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
2021-04-07 18:37 ` [edk2-devel] " Sami Mujawar
@ 2021-04-08 12:55 ` Vijayenthiran Subramaniam
0 siblings, 0 replies; 7+ messages in thread
From: Vijayenthiran Subramaniam @ 2021-04-08 12:55 UTC (permalink / raw)
To: Sami Mujawar, devel@edk2.groups.io; +Cc: Thomas Abraham, nd
[-- Attachment #1: Type: text/plain, Size: 962 bytes --]
Hi Sami,
Agree with the suggestion. Please make the changes.
Regards,
Vijay
From: "Sami Mujawar via Groups.Io" <sami.mujawar=arm.com@groups.io>
Reply to: Sami Mujawar <Sami.Mujawar@arm.com>
Date: Thursday, 8 April 2021 at 12:07 AM
To: Vijayenthiran Subramaniam <Vijayenthiran.Subramaniam@arm.com>, "devel@edk2.groups.io" <devel@edk2.groups.io>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH v3 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
Hi Vijay,
+#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+ ) \
+{ \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+}
This macros is again repeated in patch 3/3. I think this could be moved to Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h.
If you agree I can make this change locally before pushing this series.
Regards,
Sami Mujawar
[-- Attachment #2: Type: text/html, Size: 3335 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [edk2-platforms] [PATCH v3 3/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RD-V1-MC
2021-02-17 11:01 [edk2-platforms] [PATCH v3 0/3] Add HMAT tables for RD multi-chip platforms Vijayenthiran Subramaniam
2021-02-17 11:01 ` [edk2-platforms] [PATCH v3 1/3] Platform/ARM/SgiPkg: Add helper macros for HMAT table Vijayenthiran Subramaniam
2021-02-17 11:01 ` [edk2-platforms] [PATCH v3 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2 Vijayenthiran Subramaniam
@ 2021-02-17 11:01 ` Vijayenthiran Subramaniam
2021-04-08 14:51 ` [edk2-devel] [edk2-platforms] [PATCH v3 0/3] Add HMAT tables for RD multi-chip platforms Sami Mujawar
3 siblings, 0 replies; 7+ messages in thread
From: Vijayenthiran Subramaniam @ 2021-02-17 11:01 UTC (permalink / raw)
To: sami.mujawar, devel, leif, ardb+tianocore; +Cc: thomas.abraham
Add HMAT ACPI tables that is specific for RD-V1-MC quad-chip platform.
The latencies mentioned in the table are hypothetical values and
represents typical latency between four chips. These values are
applicable only for RD-V1-MC quad-chip fixed virtual and should not be
reused for other platforms.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 153 ++++++++++++++++++++
2 files changed, 155 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
index 051825993af0..04edfc487738 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,7 @@ [Sources]
Iort.aslc
Mcfg.aslc
RdV1Mc/Dsdt.asl
+ RdV1Mc/Hmat.aslc
RdV1Mc/Madt.aslc
RdV1Mc/Srat.aslc
Spcr.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
new file mode 100644
index 000000000000..c47633eb4dd3
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
@@ -0,0 +1,153 @@
+/** @file
+* Heterogeneous Memory Attribute Table (HMAT)
+*
+* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <SgiAcpiHeader.h>
+#include <SgiPlatform.h>
+
+#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
+#define INITATOR_PROXIMITY_DOMAIN_CNT 4
+#define TARGET_PROXIMITY_DOMAIN_CNT 4
+
+//
+// HMAT Table
+//
+#pragma pack (1)
+
+typedef struct InitiatorTargetProximityMatrix {
+ UINT32 InitatorProximityDomain[INITATOR_PROXIMITY_DOMAIN_CNT];
+ UINT32 TargetProximityDomain[TARGET_PROXIMITY_DOMAIN_CNT];
+ UINT16 MatrixEntry[INITATOR_PROXIMITY_DOMAIN_CNT * TARGET_PROXIMITY_DOMAIN_CNT];
+} INITIATOR_TARGET_PROXIMITY_MATRIX;
+
+typedef struct {
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
+ INITIATOR_TARGET_PROXIMITY_MATRIX Matrix;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache2;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache3;
+} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
+
+#pragma pack ()
+
+#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+ ) \
+{ \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+}
+
+EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
+ // Header
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ ),
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ },
+
+ // Memory Proximity Domain
+ {
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x0, 0x0),
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x1, 0x1),
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x2, 0x2),
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x3, 0x3),
+ },
+
+ // Latency Info
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+ 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ {
+ {0, 1, 2, 3},
+ {0, 1, 2, 3},
+ {
+ //
+ // The latencies mentioned in this table are hypothetical values and
+ // represents typical latency between four chips. These values are
+ // applicable only for RD-V1-MC quad-chip fixed virtual platform and
+ // should not be reused for other platforms.
+ //
+ 10, 20, 20, 20,
+ 20, 10, 20, 20,
+ 20, 20, 10, 20,
+ 20, 20, 20, 10,
+ }
+ },
+
+ // Memory Side Cache
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x0,
+ SIZE_1GB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x1,
+ SIZE_1GB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x2,
+ SIZE_1GB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x3,
+ SIZE_1GB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Hmat;
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [edk2-devel] [edk2-platforms] [PATCH v3 0/3] Add HMAT tables for RD multi-chip platforms
2021-02-17 11:01 [edk2-platforms] [PATCH v3 0/3] Add HMAT tables for RD multi-chip platforms Vijayenthiran Subramaniam
` (2 preceding siblings ...)
2021-02-17 11:01 ` [edk2-platforms] [PATCH v3 3/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RD-V1-MC Vijayenthiran Subramaniam
@ 2021-04-08 14:51 ` Sami Mujawar
3 siblings, 0 replies; 7+ messages in thread
From: Sami Mujawar @ 2021-04-08 14:51 UTC (permalink / raw)
To: Vijayenthiran Subramaniam, devel
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Thanks.
Regards,
Sami Mujawar
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^ permalink raw reply [flat|nested] 7+ messages in thread