From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mx.groups.io with SMTP id smtpd.web08.5842.1622117301445173328 for ; Thu, 27 May 2021 05:08:21 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: huawei.com, ip: 45.249.212.255, mailfrom: xiewenyi2@huawei.com) Received: from dggeml708-chm.china.huawei.com (unknown [172.30.72.55]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4FrRL62HMrz1BFTr for ; Thu, 27 May 2021 20:03:42 +0800 (CST) Received: from dggpemm000003.china.huawei.com (7.185.36.128) by dggeml708-chm.china.huawei.com (10.3.17.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Thu, 27 May 2021 20:08:17 +0800 Received: from HGH1000039998.huawei.com (10.184.68.188) by dggpemm000003.china.huawei.com (7.185.36.128) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 27 May 2021 20:08:16 +0800 From: "wenyi,xie" To: , , , CC: , Subject: [PATCH EDK2 v1 1/1] MdeModulePkg/Xhci: Fix TRT when data length is 0 Date: Thu, 27 May 2021 20:04:26 +0800 Message-ID: <1622117066-67642-2-git-send-email-xiewenyi2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1622117066-67642-1-git-send-email-xiewenyi2@huawei.com> References: <1622117066-67642-1-git-send-email-xiewenyi2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.184.68.188] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggpemm000003.china.huawei.com (7.185.36.128) X-CFilter-Loop: Reflected Content-Type: text/plain REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3418 According to xhci spec, at USB packet level, a Control Transfer consists of multiple transactions partitioned into stages: a setup stage, an optional data stage, and a terminating status stage. If Data Stage does not exist, the Transfer Type flag(TRT) should be No Data Stage. So if data length equals to 0, TRT is set to 0. Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni Signed-off-by: Wenyi Xie --- MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 13 +++++++++---- MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 13 +++++++++---- 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index dc36945962a0..7cbc9a8502ea 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -298,10 +298,15 @@ XhcCreateTransferTrb ( TrbStart->TrbCtrSetup.IOC = 1; TrbStart->TrbCtrSetup.IDT = 1; TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE; - if (Urb->Ep.Direction == EfiUsbDataIn) { - TrbStart->TrbCtrSetup.TRT = 3; - } else if (Urb->Ep.Direction == EfiUsbDataOut) { - TrbStart->TrbCtrSetup.TRT = 2; + if (Urb->DataLen > 0) { + if (Urb->Ep.Direction == EfiUsbDataIn) { + TrbStart->TrbCtrSetup.TRT = 3; + } else if (Urb->Ep.Direction == EfiUsbDataOut) { + TrbStart->TrbCtrSetup.TRT = 2; + } else { + DEBUG ((DEBUG_ERROR, "XhcCreateTransferTrb: Direction sholud be IN or OUT when Data exists!\n")); + ASSERT (FALSE); + } } else { TrbStart->TrbCtrSetup.TRT = 0; } diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c index 32d72ef03c2d..5b9892a1cbbb 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c @@ -291,10 +291,15 @@ XhcPeiCreateTransferTrb ( TrbStart->TrbCtrSetup.IOC = 1; TrbStart->TrbCtrSetup.IDT = 1; TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE; - if (Urb->Ep.Direction == EfiUsbDataIn) { - TrbStart->TrbCtrSetup.TRT = 3; - } else if (Urb->Ep.Direction == EfiUsbDataOut) { - TrbStart->TrbCtrSetup.TRT = 2; + if (Urb->DataLen > 0) { + if (Urb->Ep.Direction == EfiUsbDataIn) { + TrbStart->TrbCtrSetup.TRT = 3; + } else if (Urb->Ep.Direction == EfiUsbDataOut) { + TrbStart->TrbCtrSetup.TRT = 2; + } else { + DEBUG ((DEBUG_ERROR, "XhcPeiCreateTransferTrb: Direction sholud be IN or OUT when Data exists!\n")); + ASSERT (FALSE); + } } else { TrbStart->TrbCtrSetup.TRT = 0; } -- 2.20.1.windows.1