From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f175.google.com (mail-pg1-f175.google.com [209.85.215.175]) by mx.groups.io with SMTP id smtpd.web09.8596.1632980663944315109 for ; Wed, 29 Sep 2021 22:44:24 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=xXa64QIg; spf=pass (domain: linaro.org, ip: 209.85.215.175, mailfrom: masami.hiramatsu@linaro.org) Received: by mail-pg1-f175.google.com with SMTP id 133so5126524pgb.1 for ; Wed, 29 Sep 2021 22:44:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:user-agent:mime-version :content-transfer-encoding; bh=tE9l0+i7UWFj3Ml8UBICSodUjr9sO7Ndv4FpmTUosVA=; b=xXa64QIgSS0RYzxEWCkmpmUjeoiyjA1zHdm5GlzW4E0E6sOAFUfNdKIBZSaOggzkHj Vih1ePDTL7IDsR17vzRiXHokB3UhMvxrYGh9BsuYN8KDXwlFXTQ/5rTFLJk9lPaGwk3C MEoq6lAfouJDEaD8Aej6UuN1BWhTDukd5lKl3/P8TcfZ4fKVuZmEL9Hx96AV8+14sftV JKUvMIAW/Y6jrL7Ywz0X/mYSYgwVtpEOo7jNSIZZF599a5MVBsuQ642fS8F7MAVm5N27 TxUkiGHnlMbNlWHwiZiDuuRO/yExW49q+9J+xpE9phTBc7/Zy4ATDX5o0pzUTmZhoAZT Fb1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:user-agent :mime-version:content-transfer-encoding; bh=tE9l0+i7UWFj3Ml8UBICSodUjr9sO7Ndv4FpmTUosVA=; b=eluv1HNCezXFDLIn0sZtFXPV10FxnprjbN7Cu6aJx8gZ7a3GpMm+owgQHaX+J/daHw ZPkrz1rX1tqERQjhxp14XtEeaFilL94KahxDQnZx0MJikSCxlyLjC2jzG+tGIpbNFED3 alyU6ACLEJEHPHi0/uGjL3yJyyYW2IIHWl3YwLgqaFAd7hQTXn1T+6cc4pBIY8UyYsEB /LmU1SfhdZ9uCDGyMSt0upZ+fhtdW/k4XxHg8aIfeu7j7FSq1CfKHcp63s1LqZoTNKkD MQC4yhkurn9mrP1ntQrxATR0knx8gBj/HZG6PGKnmwj4iEtY+blh/TnDD7GMPN+NeVOs 7IIw== X-Gm-Message-State: AOAM532Nbq6ySQrVTbNHZEFQ+w9RwYvo47CPH22lw2gTjZ+hE0bcZ5GD lbwx36+kGizGJuHKxLGKsdAnsA== X-Google-Smtp-Source: ABdhPJwFl8oAxbMeKzCIyM6XwEBHzxZ/e2zXyXpgJOi6yqwxVZZ3ApWmgffI/CPXEKVuORA2hFXqdg== X-Received: by 2002:aa7:9596:0:b0:43e:48:dbeb with SMTP id z22-20020aa79596000000b0043e0048dbebmr2444390pfj.77.1632980663284; Wed, 29 Sep 2021 22:44:23 -0700 (PDT) Return-Path: Received: from localhost.localdomain (122x208x150x49.ap122.ftth.ucom.ne.jp. [122.208.150.49]) by smtp.gmail.com with ESMTPSA id v7sm1433812pff.195.2021.09.29.22.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Sep 2021 22:44:22 -0700 (PDT) From: "Masami Hiramatsu" To: Ard Biesheuvel , Leif Lindholm Cc: devel@edk2.groups.io, Kazuhiko Sakamoto Subject: [PATCH] Silicon/SynQuacerI2cDxe: Wait for bus busy Date: Thu, 30 Sep 2021 14:44:20 +0900 Message-Id: <163298066001.291769.2577514894991820447.stgit@localhost> X-Mailer: git-send-email 2.25.1 User-Agent: StGit/0.19 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit If an EFI application frequently repeats SetTime and GetTime, the I2C bus can be busy and failed to start. To fix this issue, add waiting loop for the bus busy status. (Usually, it is enough to read 3 times for checking, but for safety this sets 10 for timeout.) This also clean up the code path a bit so that it is easy to understand what should do on each combinations of BSR.BB and BCR.MSS. Signed-off-by: Masami Hiramatsu Reported-by: Kazuhiko Sakamoto Contributed-under: TianoCore Contribution Agreement 1.1 --- .../Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c | 38 ++++++++++++++------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c index 31f6e3072f..380eba8059 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c @@ -16,6 +16,8 @@ // #define WAIT_FOR_INTERRUPT_TIMEOUT 50000 +#define WAIT_FOR_BUS_BUSY_TIMEOUT 10 + /** Set the frequency for the I2C clock line. @@ -152,6 +154,7 @@ SynQuacerI2cMasterStart ( IN EFI_I2C_OPERATION *Op ) { + UINTN Timeout = WAIT_FOR_BUS_BUSY_TIMEOUT; UINT8 Bsr; UINT8 Bcr; @@ -167,24 +170,35 @@ SynQuacerI2cMasterStart ( Bsr = MmioRead8 (I2c->MmioBase + F_I2C_REG_BSR); Bcr = MmioRead8 (I2c->MmioBase + F_I2C_REG_BCR); - if ((Bsr & F_I2C_BSR_BB) && !(Bcr & F_I2C_BCR_MSS)) { - DEBUG ((DEBUG_INFO, "%a: bus is busy\n", __FUNCTION__)); - return EFI_ALREADY_STARTED; - } + if (!(Bcr & F_I2C_BCR_MSS)) { - if (Bsr & F_I2C_BSR_BB) { // Bus is busy - DEBUG ((DEBUG_INFO, "%a: Continuous Start\n", __FUNCTION__)); - MmioWrite8 (I2c->MmioBase + F_I2C_REG_BCR, Bcr | F_I2C_BCR_SCC); - } else { - if (Bcr & F_I2C_BCR_MSS) { - DEBUG ((DEBUG_WARN, - "%a: is not in master mode\n", __FUNCTION__)); - return EFI_DEVICE_ERROR; + if (Bsr & F_I2C_BSR_BB) { // Bus is busy + do { + Bsr = MmioRead8 (I2c->MmioBase + F_I2C_REG_BSR); + } while (Timeout-- && (Bsr & F_I2C_BSR_BB)); + + if (Bsr & F_I2C_BSR_BB) { + DEBUG ((DEBUG_INFO, "%a: bus is busy\n", __FUNCTION__)); + return EFI_ALREADY_STARTED; + } } + DEBUG ((DEBUG_INFO, "%a: Start Condition\n", __FUNCTION__)); MmioWrite8 (I2c->MmioBase + F_I2C_REG_BCR, Bcr | F_I2C_BCR_MSS | F_I2C_BCR_INTE | F_I2C_BCR_BEIE); + + } else { // F_I2C_BCR_MSS is set + + if (!(Bsr & F_I2C_BSR_BB)) { + DEBUG ((DEBUG_WARN, + "%a: is not in master mode\n", __FUNCTION__)); + return EFI_DEVICE_ERROR; + } + + DEBUG ((DEBUG_INFO, "%a: Continuous Start\n", __FUNCTION__)); + MmioWrite8 (I2c->MmioBase + F_I2C_REG_BCR, Bcr | F_I2C_BCR_SCC); } + return EFI_SUCCESS; }