From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id B74DFD81111 for ; Mon, 11 Mar 2024 13:16:15 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=UO/UnYMGKPjk4Yj8IhT2n7hCv9FihVuTa4gScWufJbg=; c=relaxed/simple; d=groups.io; h=Subject:To:From:User-Agent:MIME-Version:Date:References:In-Reply-To:Message-ID:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type; s=20240206; t=1710162974; v=1; b=0x31ymgFhSWL3CTRPo3mFnty+q2mzRoCqCnRqdCbsNZRGeCVmWctO4PZM5Qv825oMJ7hcAub ntnIIxsPT34x5O8+Th2LBy1CgIVHxi/xIYqSybl6ZwuEu1PgqNxCV/NSNz5cF+P0AKyqSNbgfaf Nhob3Aw72BrgIdypJmP0CtEJWD0ZjaefX7mRe92uo0coxObdCwciLg8KMILEv+AqieCKhzjv/eH kCxJAivrA3w76ezzaPsE6np/iGFrCZTgL4NHW8O7L3166zjO+of7llnfIcSjcMVNevCE4rzeICA fDGZLBod/75pRodk40bSPaslYmCAFx0ant3HQAd1wqagw== X-Received: by 127.0.0.2 with SMTP id OiumYY7687511xQwGxHEkEgv; Mon, 11 Mar 2024 06:16:14 -0700 Subject: Re: [edk2-devel] [edk2-platforms][PATCH v4 8/8] Platform/Sgi: Add CPPC support for RD-Fremont platform To: Prabin CA ,devel@edk2.groups.io From: "Prabin CA" X-Originating-Location: Bengaluru, Karnataka, IN (217.140.105.53) X-Originating-Platform: Windows Chrome 122 User-Agent: GROUPS.IO Web Poster MIME-Version: 1.0 Date: Mon, 11 Mar 2024 06:16:14 -0700 References: <20240301163231.2889922-9-prabin.ca@arm.com> In-Reply-To: <20240301163231.2889922-9-prabin.ca@arm.com> Message-ID: <16720.1710162973978029263@groups.io> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prabin.ca@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: r1pf3UyZEVebv1QOuLcicZaQx7686176AA= Content-Type: multipart/alternative; boundary="hBLc143CceE3xaw3OcLd" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=0x31ymgF; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none) --hBLc143CceE3xaw3OcLd Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Hi Levi, Thank you for taking the time to review these patches and providing correct= ions. For RD platforms, We don't have any performance limited register. During CP= PC testing with Linux as the OS, we've observed that Linux utilizes only th= e performance set level channel and does not utilize the performance limit = set channels. Even when we attempt to set the performance limit from Linux = sysfs, the kernel handles this internally without forwarding any limit set = requests to the platform firmware. Consequently, as these registers are opt= ional, we are not using these channels. Looking ahead to potential future i= mplementations, it's anticipated that the performance limited register will= come into play. That's why we've included the performance limited register= . if you have any suggestions, please do share. The decision to use the fast channel address was influenced by potentially = misleading information found in the FFH specification v1.2, under chapter '= B.2.2 Performance Controls', where the performance limited register address= was indicated as the next address after the 'Desired Performance Register'= . We've now updated the _CPC object with a value address of 0 for the perfo= rmance limited register (we will make the similar changes for older platfor= ms as well and post as a new series). Please do let us know if you have any= suggestions on using any specific register for the performance limited reg= ister. Your input would be greatly appreciated. Thanks, Prabin CA -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116623): https://edk2.groups.io/g/devel/message/116623 Mute This Topic: https://groups.io/mt/104668523/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --hBLc143CceE3xaw3OcLd Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable
Hi Levi,
Thank you for taking the time to review these patches and providing co= rrections. 
 
For RD platforms, We don't have any performance limited register. Duri= ng CPPC testing with Linux as the OS, we've observed that Linux utilizes on= ly the performance set level channel and does not utilize the performance l= imit set channels. Even when we attempt to set the performance limit from L= inux sysfs, the kernel handles this internally without forwarding any limit= set requests to the platform firmware. Consequently, as these registers ar= e optional, we are not using these channels. Looking ahead to potential fut= ure implementations, it's anticipated that the performance limited register= will come into play. That's why we've included the performance limited reg= ister. if you have any suggestions, please do share.
 
The decision to use the fast channel address was influenced by potenti= ally misleading information found in the FFH specification v1.2, under chap= ter 'B.2.2 Performance Controls', where the performance limited register ad= dress was indicated as the next address after the 'Desired Performance Regi= ster'. We've now updated the _CPC object with a value address of 0 for the = performance limited register (we will make the similar changes for older pl= atforms as well and post as a new series). Please do let us know if you hav= e any suggestions on using any specific register for the performance limite= d register. Your input would be greatly appreciated.
 
Thanks,
Prabin CA
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