[edk2-devel] [PATCH v2 0/4] RISC-V: Add support for Sstc extension

[edk2-devel] [PATCH v2 0/4] RISC-V: Add support for Sstc extension

[Sunil V L]

This series adds the support for RISC-V Sstc extension in EDK2 timer
implementation. Sstc extension allows S-mode software to program the
timer directly without using SBI calls.

Currently, PCD variable is used to detect whether feature is enabled. By
default the feature is enabled and platforms need to set the PCD to
disable the feature if Sstc is not supported.

For RiscVVirtQemu, it is disabled by default (until extension discovery
feature is enabled).

Changes since v1:
	1) Updated "PATCH 3" to address Laszlo's comments.
	2) Updated RB tag for PATCH 4.

Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Sunil V L (4):
  MdePkg.dec: RISC-V: Define override bit for Sstc extension
  MdePkg/BaseLib: RISC-V: Add function to update stimecmp register
  UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc
  OvmfPkg/RiscVVirt: Override Sstc extension

 MdePkg/MdePkg.dec                             |  2 +
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
 .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf |  1 +
 MdePkg/Include/Library/BaseLib.h              |  5 ++
 .../Include/Register/RiscV64/RiscVEncoding.h  |  3 ++
 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h         |  2 +
 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c         | 49 +++++++++++++++++--
 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S    |  7 +++
 8 files changed, 67 insertions(+), 4 deletions(-)

-- 
2.34.1



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[edk2-devel] [PATCH v2 1/4] MdePkg.dec: RISC-V: Define override bit for Sstc extension

[Sunil V L]

Define the BIT 1 as the override bit for Sstc extension. This will be
used by the timer driver to decide whether to use SBI calls or direct
CSR access to configure the timer.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 MdePkg/MdePkg.dec | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 2ee112cc087a..0459418906f8 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -2405,6 +2405,8 @@ [PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]
   # Configurability to override RISC-V CPU Features
   # BIT 0 = Cache Management Operations. This bit is relevant only if
   # previous stage has feature enabled and user wants to disable it.
+  # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only if
+  # previous stage has feature enabled and user wants to disable it.
   #
   gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
 
-- 
2.34.1



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Re: [edk2-devel] [PATCH v2 1/4] MdePkg.dec: RISC-V: Define override bit for Sstc extension

[Andrei Warkentin]

Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>

> -----Original Message-----
> From: Sunil V L <sunilvl@ventanamicro.com>
> Sent: Monday, January 8, 2024 5:37 AM
> To: devel@edk2.groups.io
> Cc: Sunil V L <sunilvl@ventanamicro.com>; Gao, Liming
> <gaoliming@byosoft.com.cn>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>;
> Warkentin, Andrei <andrei.warkentin@intel.com>
> Subject: [PATCH v2 1/4] MdePkg.dec: RISC-V: Define override bit for Sstc
> extension
> 
> Define the BIT 1 as the override bit for Sstc extension. This will be used by the
> timer driver to decide whether to use SBI calls or direct CSR access to configure
> the timer.
> 
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  MdePkg/MdePkg.dec | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index
> 2ee112cc087a..0459418906f8 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -2405,6 +2405,8 @@ [PcdsFixedAtBuild.RISCV64,
> PcdsPatchableInModule.RISCV64]
>    # Configurability to override RISC-V CPU Features
>    # BIT 0 = Cache Management Operations. This bit is relevant only if
>    # previous stage has feature enabled and user wants to disable it.
> +  # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only
> + if  # previous stage has feature enabled and user wants to disable it.
>    #
> 
> gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|
> UINT64|0x69
> 
> --
> 2.34.1



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[edk2-devel] [PATCH v2 2/4] MdePkg/BaseLib: RISC-V: Add function to update stimecmp register

[Sunil V L]

stimecmp is a CSR supported only when Sstc extension is supported by the
platform. This register can be used to set the timer interrupt directly in
S-mode instead of going via SBI call. Add a function to update this
register.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 MdePkg/Include/Library/BaseLib.h                | 5 +++++
 MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 3 +++
 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S      | 7 +++++++
 3 files changed, 15 insertions(+)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index b71e47f41b7f..ca0d06c7f335 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -191,6 +191,11 @@ RiscVReadTimer (
   VOID
   );
 
+VOID
+RiscVSetSupervisorTimeCompareRegister (
+  IN UINT64
+  );
+
 VOID
 RiscVEnableTimerInterrupt (
   VOID
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
index 2bde8db478ff..8ccdea2f4fcd 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -96,6 +96,9 @@
 /* Supervisor Protection and Translation */
 #define CSR_SATP  0x180
 
+/* Sstc extension */
+#define CSR_STIMECMP  0x14D
+
 /* Trap/Exception Causes */
 #define CAUSE_MISALIGNED_FETCH          0x0
 #define CAUSE_FETCH_ACCESS              0x1
diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
index 39a06efa51ef..36781c29c0b9 100644
--- a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
+++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
@@ -21,3 +21,10 @@
 ASM_FUNC (RiscVReadTimer)
     csrr a0, CSR_TIME
     ret
+
+//
+// Set Supervisor Time Compare Register
+//
+ASM_FUNC (RiscVSetSupervisorTimeCompareRegister)
+    csrw  CSR_STIMECMP, a0
+    ret
-- 
2.34.1



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Re: [edk2-devel] [PATCH v2 2/4] MdePkg/BaseLib: RISC-V: Add function to update stimecmp register

[Andrei Warkentin]

Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>

> -----Original Message-----
> From: Sunil V L <sunilvl@ventanamicro.com>
> Sent: Monday, January 8, 2024 5:37 AM
> To: devel@edk2.groups.io
> Cc: Sunil V L <sunilvl@ventanamicro.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>;
> Liu, Zhiguang <zhiguang.liu@intel.com>; Warkentin, Andrei
> <andrei.warkentin@intel.com>
> Subject: [PATCH v2 2/4] MdePkg/BaseLib: RISC-V: Add function to update
> stimecmp register
> 
> stimecmp is a CSR supported only when Sstc extension is supported by the
> platform. This register can be used to set the timer interrupt directly in S-mode
> instead of going via SBI call. Add a function to update this register.
> 
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  MdePkg/Include/Library/BaseLib.h                | 5 +++++
>  MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 3 +++
>  MdePkg/Library/BaseLib/RiscV64/ReadTimer.S      | 7 +++++++
>  3 files changed, 15 insertions(+)
> 
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index b71e47f41b7f..ca0d06c7f335 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -191,6 +191,11 @@ RiscVReadTimer (
>    VOID
>    );
> 
> +VOID
> +RiscVSetSupervisorTimeCompareRegister (
> +  IN UINT64
> +  );
> +
>  VOID
>  RiscVEnableTimerInterrupt (
>    VOID
> diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> index 2bde8db478ff..8ccdea2f4fcd 100644
> --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> @@ -96,6 +96,9 @@
>  /* Supervisor Protection and Translation */  #define CSR_SATP  0x180
> 
> +/* Sstc extension */
> +#define CSR_STIMECMP  0x14D
> +
>  /* Trap/Exception Causes */
>  #define CAUSE_MISALIGNED_FETCH          0x0
>  #define CAUSE_FETCH_ACCESS              0x1
> diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> index 39a06efa51ef..36781c29c0b9 100644
> --- a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> @@ -21,3 +21,10 @@
>  ASM_FUNC (RiscVReadTimer)
>      csrr a0, CSR_TIME
>      ret
> +
> +//
> +// Set Supervisor Time Compare Register // ASM_FUNC
> +(RiscVSetSupervisorTimeCompareRegister)
> +    csrw  CSR_STIMECMP, a0
> +    ret
> --
> 2.34.1



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[edk2-devel] [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc

[Sunil V L]

Sstc extension allows to program the timer and receive the interrupt
without using an SBI call. This reduces the latency to generate the timer
interrupt. So, detect whether Sstc extension is supported and use the
stimecmp register directly to program the timer interrupt.

Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf |  1 +
 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h         |  2 +
 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c         | 49 +++++++++++++++++--
 3 files changed, 49 insertions(+), 3 deletions(-)

diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
index aba660186dc0..f2a2cf12caef 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
@@ -41,6 +41,7 @@ [Sources.RISCV64]
   Timer.c
 
 [Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride           ## CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency  ## CONSUMES
 
 [Protocols]
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
index 9b3542230cb5..067bbd29f377 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
@@ -26,6 +26,8 @@
 //
 #define DEFAULT_TIMER_TICK_DURATION  100000
 
+#define RISCV_CPU_FEATURE_SSTC_BITMASK  BIT1
+
 extern VOID
 RiscvSetTimerPeriod (
   UINT32  TimerPeriod
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
index 30e48061cd06..216f48a52931 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
@@ -44,6 +44,45 @@ STATIC EFI_TIMER_NOTIFY  mTimerNotifyFunction;
 STATIC UINT64  mTimerPeriod     = 0;
 STATIC UINT64  mLastPeriodStart = 0;
 
+//
+// Sstc support
+//
+STATIC BOOLEAN  mSstcEnabled = FALSE;
+
+/**
+  Program the timer.
+
+  Program either using stimecmp (when Sstc extension is enabled) or using SBI
+  TIME call.
+
+  @param NextValue             Core tick value the timer should expire.
+**/
+STATIC
+VOID
+RiscVProgramTimer (
+  UINT64  NextValue
+  )
+{
+  if (mSstcEnabled) {
+    RiscVSetSupervisorTimeCompareRegister (NextValue);
+  } else {
+    SbiSetTimer (NextValue);
+  }
+}
+
+/**
+  Check whether Sstc is enabled in PCD.
+
+**/
+STATIC
+BOOLEAN
+RiscVIsSstcEnabled (
+  VOID
+  )
+{
+  return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_SSTC_BITMASK) != 0);
+}
+
 /**
   Timer Interrupt Handler.
 
@@ -94,7 +133,7 @@ TimerInterruptHandler (
                          ),
                        1000000u
                        );  // convert to tick
-  SbiSetTimer (PeriodStart);
+  RiscVProgramTimer (PeriodStart);
   RiscVEnableTimerInterrupt (); // enable SMode timer int
   gBS->RestoreTPL (OriginalTPL);
 }
@@ -197,8 +236,7 @@ TimerDriverSetTimerPeriod (
                          ),
                        1000000u
                        ); // convert to tick
-  SbiSetTimer (PeriodStart);
-
+  RiscVProgramTimer (PeriodStart);
   mCpu->EnableInterrupt (mCpu);
   RiscVEnableTimerInterrupt (); // enable SMode timer int
   return EFI_SUCCESS;
@@ -282,6 +320,11 @@ TimerDriverInitialize (
   //
   mTimerNotifyFunction = NULL;
 
+  if (RiscVIsSstcEnabled ()) {
+    mSstcEnabled = TRUE;
+    DEBUG ((DEBUG_INFO, "TimerDriverInitialize: Timer interrupt is via Sstc extension\n"));
+  }
+
   //
   // Make sure the Timer Architectural Protocol is not already installed in the system
   //
-- 
2.34.1



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Re: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc

[Laszlo Ersek]

On 1/8/24 12:36, Sunil V L wrote:
> Sstc extension allows to program the timer and receive the interrupt
> without using an SBI call. This reduces the latency to generate the timer
> interrupt. So, detect whether Sstc extension is supported and use the
> stimecmp register directly to program the timer interrupt.
> 
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf |  1 +
>  UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h         |  2 +
>  UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c         | 49 +++++++++++++++++--
>  3 files changed, 49 insertions(+), 3 deletions(-)
> 
> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> index aba660186dc0..f2a2cf12caef 100644
> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> @@ -41,6 +41,7 @@ [Sources.RISCV64]
>    Timer.c
>  
>  [Pcd]
> +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride           ## CONSUMES
>    gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency  ## CONSUMES
>  
>  [Protocols]
> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> index 9b3542230cb5..067bbd29f377 100644
> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> @@ -26,6 +26,8 @@
>  //
>  #define DEFAULT_TIMER_TICK_DURATION  100000
>  
> +#define RISCV_CPU_FEATURE_SSTC_BITMASK  BIT1
> +
>  extern VOID
>  RiscvSetTimerPeriod (
>    UINT32  TimerPeriod
> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> index 30e48061cd06..216f48a52931 100644
> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> @@ -44,6 +44,45 @@ STATIC EFI_TIMER_NOTIFY  mTimerNotifyFunction;
>  STATIC UINT64  mTimerPeriod     = 0;
>  STATIC UINT64  mLastPeriodStart = 0;
>  
> +//
> +// Sstc support
> +//
> +STATIC BOOLEAN  mSstcEnabled = FALSE;
> +
> +/**
> +  Program the timer.
> +
> +  Program either using stimecmp (when Sstc extension is enabled) or using SBI
> +  TIME call.
> +
> +  @param NextValue             Core tick value the timer should expire.
> +**/
> +STATIC
> +VOID
> +RiscVProgramTimer (
> +  UINT64  NextValue
> +  )
> +{
> +  if (mSstcEnabled) {
> +    RiscVSetSupervisorTimeCompareRegister (NextValue);
> +  } else {
> +    SbiSetTimer (NextValue);
> +  }
> +}
> +
> +/**
> +  Check whether Sstc is enabled in PCD.
> +
> +**/
> +STATIC
> +BOOLEAN
> +RiscVIsSstcEnabled (
> +  VOID
> +  )
> +{
> +  return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_SSTC_BITMASK) != 0);
> +}
> +
>  /**
>    Timer Interrupt Handler.
>  
> @@ -94,7 +133,7 @@ TimerInterruptHandler (
>                           ),
>                         1000000u
>                         );  // convert to tick
> -  SbiSetTimer (PeriodStart);
> +  RiscVProgramTimer (PeriodStart);
>    RiscVEnableTimerInterrupt (); // enable SMode timer int
>    gBS->RestoreTPL (OriginalTPL);
>  }
> @@ -197,8 +236,7 @@ TimerDriverSetTimerPeriod (
>                           ),
>                         1000000u
>                         ); // convert to tick
> -  SbiSetTimer (PeriodStart);
> -
> +  RiscVProgramTimer (PeriodStart);
>    mCpu->EnableInterrupt (mCpu);
>    RiscVEnableTimerInterrupt (); // enable SMode timer int
>    return EFI_SUCCESS;
> @@ -282,6 +320,11 @@ TimerDriverInitialize (
>    //
>    mTimerNotifyFunction = NULL;
>  
> +  if (RiscVIsSstcEnabled ()) {
> +    mSstcEnabled = TRUE;
> +    DEBUG ((DEBUG_INFO, "TimerDriverInitialize: Timer interrupt is via Sstc extension\n"));
> +  }
> +
>    //
>    // Make sure the Timer Architectural Protocol is not already installed in the system
>    //

Reviewed-by: Laszlo Ersek <lersek@redhat.com>



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Re: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc

[Dhaval Sharma]

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Reviewed-by: Dhaval Sharma <dhaval@...>


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Re: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc

[Andrei Warkentin]

Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>

> -----Original Message-----
> From: Sunil V L <sunilvl@ventanamicro.com>
> Sent: Monday, January 8, 2024 5:37 AM
> To: devel@edk2.groups.io
> Cc: Sunil V L <sunilvl@ventanamicro.com>; Gerd Hoffmann
> <kraxel@redhat.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Laszlo
> Ersek <lersek@redhat.com>; Ni, Ray <ray.ni@intel.com>; Warkentin, Andrei
> <andrei.warkentin@intel.com>
> Subject: [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for
> Sstc
> 
> Sstc extension allows to program the timer and receive the interrupt without
> using an SBI call. This reduces the latency to generate the timer interrupt. So,
> detect whether Sstc extension is supported and use the stimecmp register
> directly to program the timer interrupt.
> 
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf |  1 +
>  UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h         |  2 +
>  UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c         | 49 +++++++++++++++++--
>  3 files changed, 49 insertions(+), 3 deletions(-)
> 
> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> index aba660186dc0..f2a2cf12caef 100644
> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> @@ -41,6 +41,7 @@ [Sources.RISCV64]
>    Timer.c
> 
>  [Pcd]
> +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride           ## CONSUMES
>    gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency  ##
> CONSUMES
> 
>  [Protocols]
> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> index 9b3542230cb5..067bbd29f377 100644
> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> @@ -26,6 +26,8 @@
>  //
>  #define DEFAULT_TIMER_TICK_DURATION  100000
> 
> +#define RISCV_CPU_FEATURE_SSTC_BITMASK  BIT1
> +
>  extern VOID
>  RiscvSetTimerPeriod (
>    UINT32  TimerPeriod
> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> index 30e48061cd06..216f48a52931 100644
> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> @@ -44,6 +44,45 @@ STATIC EFI_TIMER_NOTIFY  mTimerNotifyFunction;
>  STATIC UINT64  mTimerPeriod     = 0;
>  STATIC UINT64  mLastPeriodStart = 0;
> 
> +//
> +// Sstc support
> +//
> +STATIC BOOLEAN  mSstcEnabled = FALSE;
> +
> +/**
> +  Program the timer.
> +
> +  Program either using stimecmp (when Sstc extension is enabled) or
> + using SBI  TIME call.
> +
> +  @param NextValue             Core tick value the timer should expire.
> +**/
> +STATIC
> +VOID
> +RiscVProgramTimer (
> +  UINT64  NextValue
> +  )
> +{
> +  if (mSstcEnabled) {
> +    RiscVSetSupervisorTimeCompareRegister (NextValue);
> +  } else {
> +    SbiSetTimer (NextValue);
> +  }
> +}
> +
> +/**
> +  Check whether Sstc is enabled in PCD.
> +
> +**/
> +STATIC
> +BOOLEAN
> +RiscVIsSstcEnabled (
> +  VOID
> +  )
> +{
> +  return ((PcdGet64 (PcdRiscVFeatureOverride) &
> +RISCV_CPU_FEATURE_SSTC_BITMASK) != 0); }
> +
>  /**
>    Timer Interrupt Handler.
> 
> @@ -94,7 +133,7 @@ TimerInterruptHandler (
>                           ),
>                         1000000u
>                         );  // convert to tick
> -  SbiSetTimer (PeriodStart);
> +  RiscVProgramTimer (PeriodStart);
>    RiscVEnableTimerInterrupt (); // enable SMode timer int
>    gBS->RestoreTPL (OriginalTPL);
>  }
> @@ -197,8 +236,7 @@ TimerDriverSetTimerPeriod (
>                           ),
>                         1000000u
>                         ); // convert to tick
> -  SbiSetTimer (PeriodStart);
> -
> +  RiscVProgramTimer (PeriodStart);
>    mCpu->EnableInterrupt (mCpu);
>    RiscVEnableTimerInterrupt (); // enable SMode timer int
>    return EFI_SUCCESS;
> @@ -282,6 +320,11 @@ TimerDriverInitialize (
>    //
>    mTimerNotifyFunction = NULL;
> 
> +  if (RiscVIsSstcEnabled ()) {
> +    mSstcEnabled = TRUE;
> +    DEBUG ((DEBUG_INFO, "TimerDriverInitialize: Timer interrupt is via
> + Sstc extension\n"));  }
> +
>    //
>    // Make sure the Timer Architectural Protocol is not already installed in the
> system
>    //
> --
> 2.34.1



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[edk2-devel] [PATCH v2 4/4] OvmfPkg/RiscVVirt: Override Sstc extension

[Sunil V L]

Override Sstc extension and use SBI calls itself by default for RISC-V
qemu virt platform.

Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index d3624e899e8d..6bc7c90f31dc 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -203,7 +203,7 @@ [PcdsFeatureFlag]
   gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
 
 [PcdsFixedAtBuild.common]
-  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFE
+  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFC
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
-- 
2.34.1



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Re: [edk2-devel] [PATCH v2 4/4] OvmfPkg/RiscVVirt: Override Sstc extension

[Andrei Warkentin]

Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>

> -----Original Message-----
> From: Sunil V L <sunilvl@ventanamicro.com>
> Sent: Monday, January 8, 2024 5:37 AM
> To: devel@edk2.groups.io
> Cc: Sunil V L <sunilvl@ventanamicro.com>; Warkentin, Andrei
> <andrei.warkentin@intel.com>; Ard Biesheuvel <ardb+tianocore@kernel.org>;
> Gerd Hoffmann <kraxel@redhat.com>; Yao, Jiewen <jiewen.yao@intel.com>;
> Laszlo Ersek <lersek@redhat.com>
> Subject: [PATCH v2 4/4] OvmfPkg/RiscVVirt: Override Sstc extension
> 
> Override Sstc extension and use SBI calls itself by default for RISC-V qemu virt
> platform.
> 
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
> ---
>  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> index d3624e899e8d..6bc7c90f31dc 100644
> --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> @@ -203,7 +203,7 @@ [PcdsFeatureFlag]
>    gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> 
>  [PcdsFixedAtBuild.common]
> -  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFE
> +
> gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFC
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
> --
> 2.34.1



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Re: [edk2-devel] [PATCH v2 0/4] RISC-V: Add support for Sstc extension

[Sunil V L]

On Mon, Jan 08, 2024 at 05:06:46PM +0530, Sunil V L wrote:
> This series adds the support for RISC-V Sstc extension in EDK2 timer
> implementation. Sstc extension allows S-mode software to program the
> timer directly without using SBI calls.
> 
> Currently, PCD variable is used to detect whether feature is enabled. By
> default the feature is enabled and platforms need to set the PCD to
> disable the feature if Sstc is not supported.
> 
> For RiscVVirtQemu, it is disabled by default (until extension discovery
> feature is enabled).
> 
> Changes since v1:
> 	1) Updated "PATCH 3" to address Laszlo's comments.
> 	2) Updated RB tag for PATCH 4.
> 
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> 
Thank you very much for reviews!. Merged as #5232.

Thanks,
Sunil


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