[PATCH v1 0/3] Enable RISC-V architecture for RISC-V EDK2 CI.

[PATCH v1 0/3] Enable RISC-V architecture for RISC-V EDK2 CI.

[Abner Chang]

Enable EDK2 CI test on RISC-V architecture.

BZ for entire RISC-V edk2 port,
https://bugzilla.tianocore.org/show_bug.cgi?id=2672

These commits are verified by below PR,
https://github.com/tianocore/edk2/pull/512

Abner Chang (3):
  BaseTools: Enable RISC-V architecture for RISC-V EDK2 CI.
  .azurepipelines: Add RISC-V architecture on RISC-V EDK2 CI.
  .pytool: Add RISC-V architecture on RISC-V EDK2 CI.

 .azurepipelines/Ubuntu-GCC5.yml               |  3 +-
 .pytool/CISettings.py                         |  9 ++++-
 .../Bin/gcc_riscv64_unknown_ext_dep.yaml      | 22 +++++++++++
 .../LinuxGcc5ToolChain/LinuxGcc5ToolChain.py  | 38 +++++++++++++++++++
 4 files changed, 69 insertions(+), 3 deletions(-)
 create mode 100644 BaseTools/Bin/gcc_riscv64_unknown_ext_dep.yaml

-- 
2.25.0

[PATCH v1 2/3] .azurepipelines: Enable RISC-V architecture for RISC-V EDK2 CI.

[Abner Chang]

Add RISC-V architecture on RISC-V EDK2 CI.

Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
---
 .azurepipelines/Ubuntu-GCC5.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.azurepipelines/Ubuntu-GCC5.yml b/.azurepipelines/Ubuntu-GCC5.yml
index a26a3a2cb2..7cd67c98da 100644
--- a/.azurepipelines/Ubuntu-GCC5.yml
+++ b/.azurepipelines/Ubuntu-GCC5.yml
@@ -2,6 +2,7 @@
 # Azure Pipeline build file for a build using ubuntu and GCC5
 #
 # Copyright (c) Microsoft Corporation.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 trigger:
@@ -14,5 +15,5 @@ jobs:
   parameters:
     tool_chain_tag: 'GCC5'
     vm_image: 'ubuntu-latest'
-    arch_list: "IA32,X64,ARM,AARCH64"
+    arch_list: "IA32,X64,ARM,AARCH64,RISCV64"
 
-- 
2.25.0

[PATCH v1 3/3] .pytool: Enable RISC-V architecture for RISC-V EDK2 CI.

[Abner Chang]

Add RISC-V architecture on RISC-V EDK2 CI testing.

Signed-off-by: Abner Chang <abner.chang@hpe.com>

Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
---
 .pytool/CISettings.py | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/.pytool/CISettings.py b/.pytool/CISettings.py
index 79593d9dc5..0111565ef8 100644
--- a/.pytool/CISettings.py
+++ b/.pytool/CISettings.py
@@ -1,6 +1,7 @@
 # @file
 #
 # Copyright (c) Microsoft Corporation.
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 import os
@@ -54,10 +55,12 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
 
     def GetArchitecturesSupported(self):
         ''' return iterable of edk2 architectures supported by this build '''
-        return ("IA32",
+        return (
+                "IA32",
                 "X64",
                 "ARM",
-                "AARCH64")
+                "AARCH64",
+                "RISCV64")
 
     def GetTargetsSupported(self):
         ''' return iterable of edk2 target tags supported by this build '''
@@ -130,6 +133,8 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
                 scopes += ("gcc_aarch64_linux",)
             if "ARM" in self.ActualArchitectures:
                 scopes += ("gcc_arm_linux",)
+            if "RISCV64" in self.ActualArchitectures:
+                scopes += ("gcc_riscv64_unknown",)
 
         return scopes
 
-- 
2.25.0

Re: [edk2-devel] [PATCH v1 0/3] Enable RISC-V architecture for RISC-V EDK2 CI.

[Sean]

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Please run a a test PR with this patchset?  I would like to see how it impacts the build times.
Patche series look fine to me.

Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>

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Re: [edk2-devel] [PATCH v1 0/3] Enable RISC-V architecture for RISC-V EDK2 CI.

[Abner Chang]

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Here is the test PR based on the latest edk2 master with this patch set.

Thanks for reviewing this.

From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Sean via groups.io
Sent: Saturday, April 25, 2020 11:36 AM
To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v1 0/3] Enable RISC-V architecture for RISC-V EDK2 CI.

Please run a a test PR with this patchset?  I would like to see how it impacts the build times.
Patche series look fine to me.

Reviewed-by: Sean Brogan <sean.brogan@microsoft.com<mailto:sean.brogan@microsoft.com>>


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