From mboxrd@z Thu Jan 1 00:00:00 1970 Subject: Re: [edk2-devel] [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support To: PierreGondois ,devel@edk2.groups.io From: "Khasim Mohammed" X-Originating-Location: Bengaluru, Karnataka, IN (217.140.105.53) X-Originating-Platform: Linux Firefox 72 User-Agent: GROUPS.IO Web Poster MIME-Version: 1.0 Date: Mon, 06 Dec 2021 02:27:23 -0800 References: In-Reply-To: Message-ID: <19086.1638786443971973436@groups.io> Content-Type: multipart/alternative; boundary="p1o7AM2dTMo9IzP4KeJs" --p1o7AM2dTMo9IzP4KeJs Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Tue, Nov 30, 2021 at 09:06 AM, PierreGondois wrote: Hi Pierre, >=20 > Hi Khasim, >=20 > On 11/23/21 1:26 PM, Khasim Mohammed via groups.io wrote: >=20 >> This patch enables CCIX root complex support by updating >> the root complex node info in PciHostBridge library >> and enabling PciSegment library for N1Sdp. >>=20 >> Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28 >> Signed-off-by: Khasim Syed Mohammed >> --- >> .../ConfigurationManagerDxe.inf | 3 +- >> Platform/ARM/N1Sdp/N1SdpPlatform.dec | 3 - >> Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 3 +- >> .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++-- >> .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++- >> .../Library/PlatformLib/PlatformLib.inf | 1 + >> .../Library/PlatformLib/PlatformLibMem.c | 4 +- >> 7 files changed, 81 insertions(+), 15 deletions(-) >>=20 >> diff --git >> a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Config= urationManagerDxe.inf >> b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Config= urationManagerDxe.inf >>=20 >> index 027a4202ff..67b0c3a0ea 100644 >> --- >> a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Config= urationManagerDxe.inf >>=20 >> +++ >> b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Config= urationManagerDxe.inf >>=20 >> @@ -76,8 +76,6 @@ >> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase >> gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate >>=20 >> - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress >> - >> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace >> gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base >>=20 >> @@ -91,6 +89,7 @@ >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin >> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize >> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec >> b/Platform/ARM/N1Sdp/N1SdpPlatform.dec >> index 2ab6c20dcc..98d2d5ba81 100644 >> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec >> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec >> @@ -34,9 +34,6 @@ >> gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 >> gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 >>=20 >> - # PCIe >> - >> gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00= 000007 >>=20 >> - >=20 > I think the "# Remote Chip PCIe" definitions also need to be removed. I removed these in v3 posted just now. >=20 > Unrelated to this, but it seems there are some hard-coded PCI values at >=20 > https://github.com/tianocore/edk2-platforms/blob/master/Platform/ARM/N1Sd= p/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c#L1050 >=20 >=20 > that are also defined as Pcds. Would it be possible to replace the hard > coded values ? Have removed the hardcoded entries and changed with PCDs. >=20 >=20 >> # External memory >> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029 >>=20 >> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc >> b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc >> index 7488bdc036..75d7871452 100644 >> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc >> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc >> @@ -75,7 +75,7 @@ >> [LibraryClasses.common.DXE_DRIVER] >> FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf >> PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciH= ostBridgeLib.inf >>=20 >> - >> PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf >>=20 >> + >> PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegment= Lib.inf >>=20 >> PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf >> PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressL= ib/PciExpressLib.inf >>=20 >>=20 >> @@ -127,7 +127,6 @@ >> gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 >>=20 >> # PCIe >> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000 >> gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 >> gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE >>=20 >> diff --git >> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c >> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c >> index 9332939f63..c3a14a6c17 100644 >> --- >> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c >> +++ >> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c >> @@ -1,7 +1,7 @@ >> /** @file >> * PCI Host Bridge Library instance for ARM Neoverse N1 platform >> * >> -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. >> +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
>> * >> * SPDX-License-Identifier: BSD-2-Clause-Patent >> * >> @@ -16,6 +16,8 @@ >> #include >> #include >>=20 >> +#define ROOT_COMPLEX_NUM 2 >> + >> GLOBAL_REMOVE_IF_UNREFERENCED >> STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = =3D { >>=20 >> L"Mem", L"I/O", L"Bus" >> @@ -28,7 +30,7 @@ typedef struct { >> } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; >> #pragma pack () >>=20 >> -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = =3D { >> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH >> mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] =3D { >> // PCIe >> { >> { >> @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH >> mEfiPciRootBridgeDevicePath[] =3D { >> 0 >> } >> } >> - } >> + }, >> + //CCIX >> + { >> + { >> + { >> + ACPI_DEVICE_PATH, >> + ACPI_DP, >> + { >> + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), >> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) >> + } >> + }, >> + EISA_PNP_ID(0x0A09), // CCIX >> + 0 >> + }, >> + { >> + END_DEVICE_PATH_TYPE, >> + END_ENTIRE_DEVICE_PATH_SUBTYPE, >> + { >> + END_DEVICE_PATH_LENGTH, >> + 0 >> + } >> + } >> + }, >> }; >>=20 >> -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { >> +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] =3D { >> { >> 0, // Segment >> 0, // Supports >> @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { >> 0 >> }, >> (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] >> - } >> + }, >> + { >> + 1, // Segment >> + 0, // Supports >> + 0, // Attributes >> + TRUE, // DmaAbove4G >> + FALSE, // NoExtendedConfigSpace >> + FALSE, // ResourceAssigned >> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes >> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, >> + { >> + // Bus >> + FixedPcdGet32 (PcdCcixBusMin), >> + FixedPcdGet32 (PcdCcixBusMax) >> + }, { >> + // Io >> + FixedPcdGet64 (PcdCcixIoBase), >> + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1 >> + }, { >> + // MemSilicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec >> + FixedPcdGet32 (PcdCcixMmio32Base), >> + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) = - >> 1 >> + }, { >> + // MemAbove4G >> + FixedPcdGet64 (PcdCcixMmio64Base), >> + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) = - >> 1 >> + }, { >> + // PMem >> + MAX_UINT64, >> + 0 >> + }, { >> + // PMemAbove4G >> + MAX_UINT64, >> + 0 >> + }, >> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] >> + }, >> }; >>=20 >> /** >> diff --git >> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.in= f >> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.in= f >> index 3ff1c592f2..3356c3ad35 100644 >> --- >> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.in= f >> +++ >> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.in= f >> @@ -1,7 +1,7 @@ >> ## @file >> # PCI Host Bridge Library instance for ARM Neoverse N1 platform. >> # >> -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. >> +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
>> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent >> # >> @@ -42,6 +42,15 @@ >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size >>=20 >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base >> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size >> + >> [Protocols] >> gEfiCpuIo2ProtocolGuid >>=20 >> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.i= nf >> b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf >> index 8e2154aadf..96e590cdd8 100644 >> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf >> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf >> @@ -43,6 +43,7 @@ >> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin >> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size >> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base >> diff --git >> a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c >> b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c >> index 1c4a445c5e..339fa07b32 100644 >> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c >> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c >> @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap ( >> VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_DEV= ICE; >>=20 >>=20 >> // PCIe ECAM Configuration Space >> - VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 >> (PcdPciExpressBaseAddress); >> - VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 >> (PcdPciExpressBaseAddress); >> + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 >> (PcdPcieExpressBaseAddress); >> + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 >> (PcdPcieExpressBaseAddress); >> VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPcieBusMax) - >> FixedPcdGet32 (PcdPcieBusMin) + 1) * >> SIZE_1MB; >=20 > --p1o7AM2dTMo9IzP4KeJs Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Tue, Nov 30, 2021 at 09:06 AM, PierreGondois wrote:
Hi Pierre,

Hi Khasim,

On 11/23/21 1:26 PM, Khasim Mohammed via = groups.io wrote:
This patch enables CCIX root complex support by updating
t= he root complex node info in PciHostBridge library
and enabling PciSeg= ment library for N1Sdp.

Change-Id: I0510b1023aec16365b614d4eaf81= 858851d9fa28
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@a= rm.com>
---
.../ConfigurationManagerDxe.inf | 3 +-
Platfo= rm/ARM/N1Sdp/N1SdpPlatform.dec | 3 -
Platform/ARM/N1Sdp/N1SdpPlatform.= dsc | 3 +-
.../PciHostBridgeLib/PciHostBridgeLib.c | 71 ++++++++++++++= +++--
.../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++-
.../Libr= ary/PlatformLib/PlatformLib.inf | 1 +
.../Library/PlatformLib/Platform= LibMem.c | 4 +-
7 files changed, 81 insertions(+), 15 deletions(-)

diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationM= anagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationMan= ager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
index 027a420= 2ff..67b0c3a0ea 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/C= onfigurationManagerDxe/ConfigurationManagerDxe.inf
+++ b/Platform/ARM/= N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.= inf
@@ -76,8 +76,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialReg= isterBase
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate

-= gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
-
gArmNeoverse= N1SocTokenSpaceGuid.PcdExtMemorySpace
gArmNeoverseN1SocTokenSpaceGuid.= PcdDramBlock2Base

@@ -91,6 +89,7 @@
gArmNeoverseN1SocTokenS= paceGuid.PcdPcieBusCount
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax=
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+ gArmNeoverseN1So= cTokenSpaceGuid.PcdPcieExpressBaseAddress
gArmNeoverseN1SocTokenSpaceG= uid.PcdPcieIoBase
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
diff --git a/Platform/= ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
ind= ex 2ab6c20dcc..98d2d5ba81 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatfor= m.dec
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
@@ -34,9 +34,6 @= @
gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001<= br />gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
- # PCIe
- gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|= 0x70000000|UINT32|0x00000007
-
I think the "# Remote Chip PCIe" definitions also need to be removed. I removed these in v3 posted just now.

Unrelated to this, but it seems there are some hard-coded PCI v= alues at

https://g= ithub.com/tianocore/edk2-platforms/blob/master/Platform/ARM/N1Sdp/Configura= tionManager/ConfigurationManagerDxe/ConfigurationManager.c#L1050
<= br />that are also defined as Pcds. Would it be possible to replace the har= d coded values ?
Have removed the hardcoded entries and changed with PCDs.

# External memory
gArmNeoverseN1SocTokenSpaceGuid.PcdExtMe= morySpace|0|UINT64|0x00000029

diff --git a/Platform/ARM/N1Sdp/N1= SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 7488bdc03= 6..75d7871452 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+= ++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -75,7 +75,7 @@
[Libr= aryClasses.common.DXE_DRIVER]
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib= .inf
PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeL= ib/PciHostBridgeLib.inf
- PciSegmentLib|MdePkg/Library/BasePciSegmentL= ibPci/BasePciSegmentLibPci.inf
+ PciSegmentLib|Silicon/ARM/NeoverseN1S= oc/Library/PciSegmentLib/PciSegmentLib.inf
PciLib|MdePkg/Library/BaseP= ciLibPciExpress/BasePciLibPciExpress.inf
PciExpressLib|Silicon/ARM/Neo= verseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf

= @@ -127,7 +127,6 @@
gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C= 0000

# PCIe
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAdd= ress|0x70000000
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
gEfi= MdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE

diff --git a/Si= licon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silic= on/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
index= 9332939f63..c3a14a6c17 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library= /PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/ARM/NeoverseN1Soc/L= ibrary/PciHostBridgeLib/PciHostBridgeLib.c
@@ -1,7 +1,7 @@
/** @f= ile
* PCI Host Bridge Library instance for ARM Neoverse N1 platform*
-* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.+* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR&g= t;
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@= @ -16,6 +16,8 @@
#include <Protocol/PciHostBridgeResourceAllocation= .h>
#include <Protocol/PciRootBridgeIo.h>

+#define= ROOT_COMPLEX_NUM 2
+
GLOBAL_REMOVE_IF_UNREFERENCED
STATIC C= HAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D {
L= "Mem", L"I/O", L"Bus"
@@ -28,7 +30,7 @@ typedef struct {
} EFI_PC= I_ROOT_BRIDGE_DEVICE_PATH;
#pragma pack ()

-STATIC EFI_PCI_= ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] =3D {
+STATIC EF= I_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM]= =3D {
// PCIe
{
{
@@ -51,10 +53,33 @@ STATIC EFI_PCI_R= OOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] =3D {
0
}}
- }
+ },
+ //CCIX
+ {
+ {
+ {
+ ACP= I_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)sizeof (ACPI_HID_DEVI= CE_PATH),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }=
+ },
+ EISA_PNP_ID(0x0A09), // CCIX
+ 0
+ },
+ {<= br />+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ = {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
= };

-STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D {
+STATIC P= CI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] =3D {
{
0, // Seg= ment
0, // Supports
@@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mP= ciRootBridge[] =3D {
0
},
(EFI_DEVICE_PATH_PROTOCOL *)&m= EfiPciRootBridgeDevicePath[0]
- }
+ },
+ {
+ 1, // Segm= ent
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4= G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned<= br />+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
= + EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ {
+ // Bus
+ FixedPcdG= et32 (PcdCcixBusMin),
+ FixedPcdGet32 (PcdCcixBusMax)
+ }, {
+ // Io
+ FixedPcdGet64 (PcdCcixIoBase),
+ FixedPcdGet64 (PcdCci= xIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
+ }, {
+ // MemSilic= on/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+ FixedPcdGet32 (PcdCcixMmio32B= ase),
+ FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio= 32Size) - 1
+ }, {
+ // MemAbove4G
+ FixedPcdGet64 (PcdCcixM= mio64Base),
+ FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCc= ixMmio64Size) - 1
+ }, {
+ // PMem
+ MAX_UINT64,
+ 0+ }, {
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
= + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
+ },=
};

/**
diff --git a/Silicon/ARM/NeoverseN1Soc/Library= /PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/= PciHostBridgeLib/PciHostBridgeLib.inf
index 3ff1c592f2..3356c3ad35 100= 644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBr= idgeLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/P= ciHostBridgeLib.inf
@@ -1,7 +1,7 @@
## @file
# PCI Host Brid= ge Library instance for ARM Neoverse N1 platform.
#
-# Copyright = (c) 2019 - 2020, ARM Limited. All rights reserved.
+# Copyright (c) 20= 19 - 2021, ARM Limited. All rights reserved.<BR>
#
# SPDX-L= icense-Identifier: BSD-2-Clause-Patent
#
@@ -42,6 +42,15 @@
= gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
gArmNeoverseN1SocTok= enSpaceGuid.PcdPcieMmio64Size

+ gArmNeoverseN1SocTokenSpaceGuid.= PcdCcixBusMin
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
+ g= ArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
+ gArmNeoverseN1SocTokenS= paceGuid.PcdCcixIoSize
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32= Base
+ gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
+ gArmNe= overseN1SocTokenSpaceGuid.PcdCcixMmio64Base
+ gArmNeoverseN1SocTokenSp= aceGuid.PcdCcixMmio64Size
+
[Protocols]
gEfiCpuIo2ProtocolGu= id

diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/Pl= atformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.i= nf
index 8e2154aadf..96e590cdd8 100644
--- a/Silicon/ARM/Neoverse= N1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1= Soc/Library/PlatformLib/PlatformLib.inf
@@ -43,6 +43,7 @@
gArmNeo= verseN1SocTokenSpaceGuid.PcdExtMemorySpace
gArmNeoverseN1SocTokenSpace= Guid.PcdPcieBusMax
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
= + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
gArmNeover= seN1SocTokenSpaceGuid.PcdPcieMmio32Base
gArmNeoverseN1SocTokenSpaceGui= d.PcdPcieMmio32Size
gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base<= br />diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib= Mem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index 1c4a445c5e..339fa07b32 100644
--- a/Silicon/ARM/NeoverseN1Soc/L= ibrary/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Li= brary/PlatformLib/PlatformLibMem.c
@@ -115,8 +115,8 @@ ArmPlatformGetV= irtualMemoryMap (
VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_= REGION_ATTRIBUTE_DEVICE;

// PCIe ECAM Configuration Space
-= VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpressBaseAd= dress);
- VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciEx= pressBaseAddress);
+ VirtualMemoryTable[++Index].PhysicalBase =3D PcdG= et64 (PcdPcieExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualB= ase =3D PcdGet64 (PcdPcieExpressBaseAddress);
VirtualMemoryTable[Index= ].Length =3D (FixedPcdGet32 (PcdPcieBusMax) -
FixedPcdGet32 (PcdPcieBu= sMin) + 1) *
SIZE_1MB;
--p1o7AM2dTMo9IzP4KeJs--