From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web08.9562.1664278058738446551 for ; Tue, 27 Sep 2022 04:27:39 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from lichao-PC (unknown [10.40.24.149]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx32sl3jJjPb0iAA--.58091S2; Tue, 27 Sep 2022 19:27:33 +0800 (CST) Date: Tue, 27 Sep 2022 19:27:33 +0800 From: "Chao Li" To: Michael D Kinney Cc: Liming Gao , Zhiguang Liu , Baoqi Zhang , "=?utf-8?Q?devel=40edk2.groups.io?=" Message-ID: <1F8DF3E6-E3A3-41BF-9A53-48BABFD03BF0@getmailspring.com> In-Reply-To: <20220927111354.4107719-30-lichao@loongson.cn> References: <20220927111354.4107719-30-lichao@loongson.cn> Subject: Re: [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code. X-Mailer: Mailspring MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bx32sl3jJjPb0iAA--.58091S2 X-Coremail-Antispam: 1UD129KBjvJXoWfGr1rAF45Cw4kGw48KryxuFg_yoWDKFyxpr 43trZrKan2gw43CF48G3s5JF15Aw4kWr4DGFZ0vw18Awn0vrykZrs0qr10gFW8urW7Ww18 WF13KF4Fk3WUAa7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPlb7Iv0xC_KF4lb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I 8E87Iv6xkF7I0E14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVAYj202 j2C_Jr0_Gr1l5I8CrVACY4xI64kE6c02F40Ex7xfMc02F40Ew4AK048IF2xKxVW8JVW5Jw Av7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY 6r1j6r4UM4x0Y48IcxkI7VAKI48JMx8GjcxK6IxK0xIIj40E5I8CrwCY1x0262kKe7AKxV WUAVWUtwCY02Avz4vE-syl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1l x2IqxVAqx4xG67AKxVWUGVWUWwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14 v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IY x2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87 Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZF pf9x07jwuc_UUUUU= X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQACCGMxll4dbgA3sV Content-Type: multipart/alternative; boundary="6332de25_66b4baed_19e08" --6332de25_66b4baed_19e08 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Hi Mike, I have converted the inline assembly code to ASM code, please review this= patch again, thanks=21 Thanks, Chao -------- On 9=E6=9C=88 27 2022, at 7:13 =E6=99=9A=E4=B8=8A, Chao Li wrote: > RE=46: https://bugzilla.tianocore.org/show=5Fbug.cgi=3Fid=3D4053 > > Support LoongArch cache related functions. > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > > Signed-off-by: Chao Li > Co-authored-by: Baoqi Zhang > --- > .../BaseSynchronizationLib.inf =7C 6 + > .../LoongArch64/AsmSynchronization.S =7C 122 +++++++++ > .../LoongArch64/Synchronization.c =7C 233 ++++++++++++++++++ > 3 files changed, 361 insertions(+) > create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/As= mSynchronization.S > create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/Sy= nchronization.c > > diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationL= ib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf= > index 02ba12961a..dd66ec1d03 100755 > --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf > +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf > =40=40 -4,6 +4,7 =40=40 > =23 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<= BR> > > =23 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.=
> =23 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All = rights reserved.
> +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> =23 > =23 SPDX-License-Identifier: BSD-2-Clause-Patent > =23 > =40=40 -82,6 +83,11 =40=40 > Synchronization.c > > RiscV64/Synchronization.S > > > +=5BSources.LOONGARCH64=5D > + Synchronization.c > + LoongArch64/Synchronization.c =7C GCC > + LoongArch64/AsmSynchronization.S =7C GCC > + > =5BPackages=5D > MdePkg/MdePkg.dec > > > diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynch= ronization.S b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynch= ronization.S > new file mode 100644 > index 0000000000..3f1b06172d > --- /dev/null > +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronizat= ion.S > =40=40 -0,0 +1,122 =40=40 > +=23-------------------------------------------------------------------= ----------- > +=23 > +=23 LoongArch synchronization ASM functions. > +=23 > +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> +=23 > +=23 SPDX-License-Identifier: BSD-2-Clause-Patent > +=23 > +=23-------------------------------------------------------------------= ----------- > + > +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncCompareExchange16) > +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncCompareExchange32) > +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncCompareExchange64) > +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncIncrement) > +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncDecrement) > + > +/** > +UINT32 > +E=46IAPI > +AsmInternalSyncCompareExchange16 ( > + IN volatile UINT32 *Ptr32, > + IN UINT64 Mask, > + IN UINT64 LocalCompareValue, > + IN UINT64 LocalExchangeValue > + ) > +**/ > +ASM=5FP=46X(AsmInternalSyncCompareExchange16): > +1: > + ll.w =24t0, =24a0, 0x0 > + and =24t1, =24t0, =24a1 > + bne =24t1, =24a2, 2f > + andn =24t1, =24t0, =24a1 > + or =24t1, =24t1, =24a3 > + sc.w =24t1, =24a0, 0x0 > + beqz =24t1, 1b > + b 3f > +2: > + dbar 0 > +3: > + move =24a0, =24t0 > + jirl =24zero, =24ra, 0 > + > +/** > +UINT32 > +E=46IAPI > +AsmInternalSyncCompareExchange32 ( > + IN volatile UINT32 *Value, > + IN UINT64 CompareValue, > + IN UINT64 ExchangeValue > + ) > +**/ > +ASM=5FP=46X(AsmInternalSyncCompareExchange32): > +1: > + ll.w =24t0, =24a0, 0x0 > + bne =24t0, =24a1, 2f > + move =24t0, =24a2 > + sc.w =24t0, =24a0, 0x0 > + beqz =24t0, 1b > + b 3f > +2: > + dbar 0 > +3: > + move =24a0, =24t0 > + jirl =24zero, =24ra, 0 > + > +/** > +UINT64 > +E=46IAPI > +AsmInternalSyncCompareExchange64 ( > + IN volatile UINT64 *Value, > + IN UINT64 CompareValue, > + IN UINT64 ExchangeValue > + ) > +**/ > +ASM=5FP=46X(AsmInternalSyncCompareExchange64): > +1: > + ll.d =24t0, =24a0, 0x0 > + bne =24t0, =24a1, 2f > + move =24t0, =24a2 > + sc.d =24t0, =24a0, 0x0 > + beqz =24t0, 1b > + b 3f > +2: > + dbar 0 > +3: > + move =24a0, =24t0 > + jirl =24zero, =24ra, 0 > + > +/** > +UINT32 > +E=46IAPI > +AsmInternalSyncIncrement ( > + IN volatile UINT32 *Value > + ) > +**/ > +ASM=5FP=46X(AsmInternalSyncIncrement): > + move =24t0, =24a0 > + dbar 0 > + ld.w =24t1, =24t0, 0x0 > + li.w =24t2, 1 > + amadd.w =24t1, =24t2, =24t0 > + > + ld.w =24a0, =24t0, 0x0 > + jirl =24zero, =24ra, 0 > + > +/** > +UINT32 > +E=46IAPI > +AsmInternalSyncDecrement ( > + IN volatile UINT32 *Value > + ) > +**/ > +ASM=5FP=46X(AsmInternalSyncDecrement): > + move =24t0, =24a0 > + dbar 0 > + ld.w =24t1, =24t0, 0x0 > + li.w =24t2, -1 > + amadd.w =24t1, =24t2, =24t0 > + > + ld.w =24a0, =24t0, 0x0 > + jirl =24zero, =24ra, 0 > +.end > diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchron= ization.c b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchroniza= tion.c > new file mode 100644 > index 0000000000..d696c8ce10 > --- /dev/null > +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization= .c > =40=40 -0,0 +1,233 =40=40 > +/** =40file > > + LoongArch synchronization functions. > + > + Copyright (c) 2022, Loongson Technology Corporation Limited. All righ= ts reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +=23include > + > +UINT32 > +E=46IAPI > +AsmInternalSyncCompareExchange16 ( > + IN volatile UINT32 *, > + IN UINT64, > + IN UINT64, > + IN UINT64 > + ); > + > +UINT32 > +E=46IAPI > +AsmInternalSyncCompareExchange32 ( > + IN volatile UINT32 *, > + IN UINT64, > + IN UINT64 > + ); > + > +UINT64 > +E=46IAPI > +AsmInternalSyncCompareExchange64 ( > + IN volatile UINT64 *, > + IN UINT64, > + IN UINT64 > + ); > + > +UINT32 > +E=46IAPI > +AsmInternalSyncIncrement ( > + IN volatile UINT32 * > + ); > + > +UINT32 > +E=46IAPI > +AsmInternalSyncDecrement ( > + IN volatile UINT32 * > + ); > + > +/** > + Performs an atomic compare exchange operation on a 16-bit > + unsigned integer. > + > + Performs an atomic compare exchange operation on the 16-bit > + unsigned integer specified by Value. If Value is equal to > + CompareValue, then Value is set to ExchangeValue and > + CompareValue is returned. If Value is not equal to > + CompareValue, then Value is returned. The compare exchange > + operation must be performed using MP safe mechanisms. > + > + =40param=5Bin=5D Value A pointer to the 16-bit value for the > + compare exchange operation. > + =40param=5Bin=5D CompareValue 16-bit value used in compare operation.= > + =40param=5Bin=5D ExchangeValue 16-bit value used in exchange operatio= n. > + > + =40return The original *Value before exchange. > + > +**/ > +UINT16 > +E=46IAPI > +InternalSyncCompareExchange16 ( > + IN volatile UINT16 *Value, > + IN UINT16 CompareValue, > + IN UINT16 ExchangeValue > + ) > +=7B > + UINT32 RetValue; > + UINT32 Shift; > + UINT64 Mask; > + UINT64 LocalCompareValue; > + UINT64 LocalExchangeValue; > + volatile UINT32 *Ptr32; > + > + /* Check that ptr is naturally aligned */ > + ASSERT (=21((UINT64)Value & (sizeof (Value) - 1))); > + > + /* Mask inputs to the correct size. */ > + Mask =3D (((=7E0UL) - (1UL << (0)) + 1) & (=7E0UL >> (64 - 1 - ((size= of (UINT16) * 8) - 1)))); > + LocalCompareValue =3D ((UINT64)CompareValue) & Mask; > + LocalExchangeValue =3D ((UINT64)ExchangeValue) & Mask; > + > + /* > + * Calculate a shift & mask that correspond to the value we wish to > + * compare & exchange within the naturally aligned 4 byte integer > + * that includes it. > + */ > + Shift =3D (UINT64)Value & 0x3; > + Shift *=3D 8; /* BITS=5FPER=5FBYTE */ > + LocalCompareValue <<=3D Shift; > + LocalExchangeValue <<=3D Shift; > + Mask <<=3D Shift; > + > + /* > + * Calculate a pointer to the naturally aligned 4 byte integer that > + * includes our byte of interest, and load its value. > + */ > + Ptr32 =3D (UINT32 *)((UINT64)Value & =7E0x3); > + > + RetValue =3D AsmInternalSyncCompareExchange16 ( > + Ptr32, > + Mask, > + LocalCompareValue, > + LocalExchangeValue > + ); > + > + return (RetValue & Mask) >> Shift; > +=7D > + > +/** > + Performs an atomic compare exchange operation on a 32-bit > + unsigned integer. > + > + Performs an atomic compare exchange operation on the 32-bit > + unsigned integer specified by Value. If Value is equal to > + CompareValue, then Value is set to ExchangeValue and > + CompareValue is returned. If Value is not equal to > + CompareValue, then Value is returned. The compare exchange > + operation must be performed using MP safe mechanisms. > + > + =40param=5Bin=5D Value A pointer to the 32-bit value for the > + compare exchange operation. > + =40param=5Bin=5D CompareValue 32-bit value used in compare operation.= > + =40param=5Bin=5D ExchangeValue 32-bit value used in exchange operatio= n. > + > + =40return The original *Value before exchange. > + > +**/ > +UINT32 > +E=46IAPI > +InternalSyncCompareExchange32 ( > + IN volatile UINT32 *Value, > + IN UINT32 CompareValue, > + IN UINT32 ExchangeValue > + ) > +=7B > + UINT32 RetValue; > + > + RetValue =3D AsmInternalSyncCompareExchange32 ( > + Value, > + CompareValue, > + ExchangeValue > + ); > + > + return RetValue; > +=7D > + > +/** > + Performs an atomic compare exchange operation on a 64-bit unsigned in= teger. > + > + Performs an atomic compare exchange operation on the 64-bit unsigned = integer specified > + by Value. If Value is equal to CompareValue, then Value is set to Exc= hangeValue and > + CompareValue is returned. If Value is not equal to CompareValue, then= Value is returned. > + The compare exchange operation must be performed using MP safe mechan= isms. > + > + =40param=5Bin=5D Value A pointer to the 64-bit value for the compare = exchange > + operation. > + =40param=5Bin=5D CompareValue 64-bit value used in compare operation.= > + =40param=5Bin=5D ExchangeValue 64-bit value used in exchange operatio= n. > + > + =40return The original *Value before exchange. > + > +**/ > +UINT64 > +E=46IAPI > +InternalSyncCompareExchange64 ( > + IN volatile UINT64 *Value, > + IN UINT64 CompareValue, > + IN UINT64 ExchangeValue > + ) > +=7B > + UINT64 RetValue; > + > + RetValue =3D AsmInternalSyncCompareExchange64 ( > + Value, > + CompareValue, > + ExchangeValue > + ); > + > + return RetValue; > +=7D > + > +/** > + Performs an atomic increment of an 32-bit unsigned integer. > + > + Performs an atomic increment of the 32-bit unsigned integer specified= by > + Value and returns the incremented value. The increment operation must= be > + performed using MP safe mechanisms. The state of the return value is = not > + guaranteed to be MP safe. > + > + =40param=5Bin=5D Value A pointer to the 32-bit value to increment. > + > + =40return The incremented value. > + > +**/ > +UINT32 > +E=46IAPI > +InternalSyncIncrement ( > + IN volatile UINT32 *Value > + ) > +=7B > + return AsmInternalSyncIncrement (Value); > +=7D > + > +/** > + Performs an atomic decrement of an 32-bit unsigned integer. > + > + Performs an atomic decrement of the 32-bit unsigned integer specified= by > + Value and returns the decrement value. The decrement operation must b= e > + performed using MP safe mechanisms. The state of the return value is = not > + guaranteed to be MP safe. > + > + =40param=5Bin=5D Value A pointer to the 32-bit value to decrement. > + > + =40return The decrement value. > + > +**/ > +UINT32 > +E=46IAPI > +InternalSyncDecrement ( > + IN volatile UINT32 *Value > + ) > +=7B > + return AsmInternalSyncDecrement (Value); > +=7D > -- > 2.27.0 > --6332de25_66b4baed_19e08 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline
Hi Mike,
I have converted the inline assembly code to ASM = code, please review this patch again, thanks=21


Thanks,
Chao
--------

On 9=E6=9C=88 27 2022, at 7:13 =E6=99=9A= =E4=B8=8A, Chao Li <lichao=40loongson.cn> wrote:
<= div>
RE=46: https://bugzilla.tianocore.org/show=5Fbug.cgi=3Fid=3D4053=

Support LoongArch cache related functions.

C= c: Michael D Kinney <michael.d.kinney=40intel.com>
Cc: Li= ming Gao <gaoliming=40byosoft.com.cn>
Cc: Zhiguang Liu &l= t;zhiguang.liu=40intel.com>

Signed-off-by: Chao Li <l= ichao=40loongson.cn>
Co-authored-by: Baoqi Zhang <zhangba= oqi=40loongson.cn>
---
.../BaseSynchronizationLib.= inf =7C 6 +
.../LoongArch64/AsmSynchronization.S =7C 122 ++++++= +++
.../LoongArch64/Synchronization.c =7C 233 +++++++++++++++++= +
3 files changed, 361 insertions(+)
create mode 1006= 44 MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S=
create mode 100644 MdePkg/Library/BaseSynchronizationLib/Loong= Arch64/Synchronization.c

diff --git a/MdePkg/Library/BaseSy= nchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchron= izationLib/BaseSynchronizationLib.inf
index 02ba12961a..dd66ec1= d03 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSync= hronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/= BaseSynchronizationLib.inf
=40=40 -4,6 +4,7 =40=40
=23= Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR= >

=23 Portions copyright (c) 2008 - 2009, Apple Inc. All= rights reserved.<BR>

=23 Copyright (c) 2020, Hewlett= Packard Enterprise Development LP. All rights reserved.<BR>
<= br>
+=23 Copyright (c) 2022, Loongson Technology Corporation Limited.= All rights reserved.<BR>

=23

=23 SPDX-= License-Identifier: BSD-2-Clause-Patent

=23

=40= =40 -82,6 +83,11 =40=40
Synchronization.c

RiscV64= /Synchronization.S



+=5BSources.LOONGARCH64=5D
=
+ Synchronization.c

+ LoongArch64/Synchronization.= c =7C GCC

+ LoongArch64/AsmSynchronization.S =7C GCC
<= br>
+

=5BPackages=5D

MdePkg/MdePkg.dec


diff --git a/MdePkg/Library/BaseSynchronizationLib/Lo= ongArch64/AsmSynchronization.S b/MdePkg/Library/BaseSynchronizationLib/Lo= ongArch64/AsmSynchronization.S
new file mode 100644
i= ndex 0000000000..3f1b06172d
--- /dev/null
+++ b/MdePk= g/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
=40=40 -0,0 +1,122 =40=40
+=23------------------------------= ------------------------------------------------
+=23
+=23 LoongArch synchronization ASM functions.
+=23
+= =23 Copyright (c) 2022, Loongson Technology Corporation Limited. All righ= ts reserved.<BR>
+=23
+=23 SPDX-License-Identif= ier: BSD-2-Clause-Patent
+=23
+=23-------------------= -----------------------------------------------------------
+
+ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncCompareExchange16)
+ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncCompareExchange32)
+ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncCompareExchange64)
= +ASM=5FGLOBAL ASM=5FP=46X(AsmInternalSyncIncrement)
+ASM=5FGLOB= AL ASM=5FP=46X(AsmInternalSyncDecrement)
+
+/**
=
+UINT32
+E=46IAPI
+AsmInternalSyncCompareExchang= e16 (
+ IN volatile UINT32 *Ptr32,
+ IN UINT64 Mask,<= /div>
+ IN UINT64 LocalCompareValue,
+ IN UINT64 LocalExcha= ngeValue
+ )
+**/
+ASM=5FP=46X(AsmInternalS= yncCompareExchange16):
+1:
+ ll.w =24t0, =24a0, 0x0
+ and =24t1, =24t0, =24a1
+ bne =24t1, =24a2, 2f
=
+ andn =24t1, =24t0, =24a1
+ or =24t1, =24t1, =24a3
<= div>+ sc.w =24t1, =24a0, 0x0
+ beqz =24t1, 1b
+ b 3f<= /div>
+2:
+ dbar 0
+3:
+ move =24a0, =24= t0
+ jirl =24zero, =24ra, 0
+
+/**
+UINT32
+E=46IAPI
+AsmInternalSyncCompareExchange32= (
+ IN volatile UINT32 *Value,
+ IN UINT64 CompareVa= lue,
+ IN UINT64 ExchangeValue
+ )
+**/
+ASM=5FP=46X(AsmInternalSyncCompareExchange32):
+1:
+ ll.w =24t0, =24a0, 0x0
+ bne =24t0, =24a1, 2f
+ move =24t0, =24a2
+ sc.w =24t0, =24a0, 0x0
+ beqz = =24t0, 1b
+ b 3f
+2:
+ dbar 0
+3:=
+ move =24a0, =24t0
+ jirl =24zero, =24ra, 0
+
+/**
+UINT64
+E=46IAPI
+AsmI= nternalSyncCompareExchange64 (
+ IN volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
+ )
+**/
+ASM=5FP=46X(AsmInternalSyncCompareExc= hange64):
+1:
+ ll.d =24t0, =24a0, 0x0
+ bn= e =24t0, =24a1, 2f
+ move =24t0, =24a2
+ sc.d =24t0, = =24a0, 0x0
+ beqz =24t0, 1b
+ b 3f
+2:
+ dbar 0
+3:
+ move =24a0, =24t0
+ ji= rl =24zero, =24ra, 0
+
+/**
+UINT32
+E=46IAPI
+AsmInternalSyncIncrement (
+ IN volatil= e UINT32 *Value
+ )
+**/
+ASM=5FP=46X(AsmIn= ternalSyncIncrement):
+ move =24t0, =24a0
+ dbar 0
+ ld.w =24t1, =24t0, 0x0
+ li.w =24t2, 1
+ am= add.w =24t1, =24t2, =24t0
+
+ ld.w =24a0, =24t0, 0x0<= /div>
+ jirl =24zero, =24ra, 0
+
+/**
+= UINT32
+E=46IAPI
+AsmInternalSyncDecrement (
+ IN volatile UINT32 *Value
+ )
+**/
+ASM= =5FP=46X(AsmInternalSyncDecrement):
+ move =24t0, =24a0
+ dbar 0
+ ld.w =24t1, =24t0, 0x0
+ li.w =24t2, -1=
+ amadd.w =24t1, =24t2, =24t0
+
+ ld.w =24= a0, =24t0, 0x0
+ jirl =24zero, =24ra, 0
+.end
diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchro= nization.c b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchroniz= ation.c
new file mode 100644
index 0000000000..d696c8= ce10
--- /dev/null
+++ b/MdePkg/Library/BaseSynchroni= zationLib/LoongArch64/Synchronization.c
=40=40 -0,0 +1,233 =40=40=
+/** =40file

+ LoongArch synchronization functio= ns.

+

+ Copyright (c) 2022, Loongson Technolo= gy Corporation Limited. All rights reserved.<BR>

+
+ SPDX-License-Identifier: BSD-2-Clause-Patent

= +

+**/

+

+=23include <Librar= y/DebugLib.h>

+

+UINT32

+E=46= IAPI

+AsmInternalSyncCompareExchange16 (

+ IN= volatile UINT32 *,

+ IN UINT64,

+ IN UINT64,=

+ IN UINT64

+ );

+

+UINT32

+E=46IAPI

+AsmInternalSyncCompareE= xchange32 (

+ IN volatile UINT32 *,

+ IN UINT= 64,

+ IN UINT64

+ );

+
+UINT64

+E=46IAPI

+AsmInternalSyncCompa= reExchange64 (

+ IN volatile UINT64 *,

+ IN U= INT64,

+ IN UINT64

+ );

+
=
+UINT32

+E=46IAPI

+AsmInternalSyncIn= crement (

+ IN volatile UINT32 *

+ );
+

+UINT32

+E=46IAPI

+Asm= InternalSyncDecrement (

+ IN volatile UINT32 *

+ );

+

+/**

+ Performs an ato= mic compare exchange operation on a 16-bit

+ unsigned integ= er.

+

+ Performs an atomic compare exchange o= peration on the 16-bit

+ unsigned integer specified by Valu= e. If Value is equal to

+ CompareValue, then Value is set t= o ExchangeValue and

+ CompareValue is returned. If Value is= not equal to

+ CompareValue, then Value is returned. The c= ompare exchange

+ operation must be performed using MP safe= mechanisms.

+

+ =40param=5Bin=5D Value A poi= nter to the 16-bit value for the

+ compare exchange operati= on.

+ =40param=5Bin=5D CompareValue 16-bit value used in co= mpare operation.

+ =40param=5Bin=5D ExchangeValue 16-bit va= lue used in exchange operation.

+

+ =40return= The original *Value before exchange.

+

+**/<= /div>
+UINT16

+E=46IAPI

+InternalSync= CompareExchange16 (

+ IN volatile UINT16 *Value,

<= div>+ IN UINT16 CompareValue,

+ IN UINT16 ExchangeValue
+ )

+=7B

+ UINT32 RetValue;
<= br>
+ UINT32 Shift;

+ UINT64 Mask;

+ UINT= 64 LocalCompareValue;

+ UINT64 LocalExchangeValue;
+ volatile UINT32 *Ptr32;

+

+ /* Check = that ptr is naturally aligned */

+ ASSERT (=21((UINT64)Valu= e & (sizeof (Value) - 1)));

+

+ /* Mask i= nputs to the correct size. */

+ Mask =3D (((=7E0UL) - (1UL = << (0)) + 1) & (=7E0UL >> (64 - 1 - ((sizeof (UINT16) * 8= ) - 1))));

+ LocalCompareValue =3D ((UINT64)CompareValue) &= amp; Mask;

+ LocalExchangeValue =3D ((UINT64)ExchangeValue)= & Mask;

+

+ /*

+ * Calcula= te a shift & mask that correspond to the value we wish to

+ * compare & exchange within the naturally aligned 4 byte integer=

+ * that includes it.

+ */

+ S= hift =3D (UINT64)Value & 0x3;

+ Shift *=3D 8; /* BITS=5F= PER=5FBYTE */

+ LocalCompareValue <<=3D Shift;
<= br>
+ LocalExchangeValue <<=3D Shift;

+ Mask <= <=3D Shift;

+

+ /*

+ * Calcu= late a pointer to the naturally aligned 4 byte integer that

+ * includes our byte of interest, and load its value.

+ *= /

+ Ptr32 =3D (UINT32 *)((UINT64)Value & =7E0x3);
=
+

+ RetValue =3D AsmInternalSyncCompareExchange16 = (

+ Ptr32,

+ Mask,

+ LocalCompa= reValue,

+ LocalExchangeValue

+ );

<= div>+

+ return (RetValue & Mask) >> Shift;
<= br>
+=7D

+

+/**

+ Performs = an atomic compare exchange operation on a 32-bit

+ unsigned= integer.

+

+ Performs an atomic compare exch= ange operation on the 32-bit

+ unsigned integer specified b= y Value. If Value is equal to

+ CompareValue, then Value is= set to ExchangeValue and

+ CompareValue is returned. If Va= lue is not equal to

+ CompareValue, then Value is returned.= The compare exchange

+ operation must be performed using M= P safe mechanisms.

+

+ =40param=5Bin=5D Value= A pointer to the 32-bit value for the

+ compare exchange o= peration.

+ =40param=5Bin=5D CompareValue 32-bit value used= in compare operation.

+ =40param=5Bin=5D ExchangeValue 32-= bit value used in exchange operation.

+

+ =40= return The original *Value before exchange.

+

+**/
+UINT32

+E=46IAPI

+Intern= alSyncCompareExchange32 (

+ IN volatile UINT32 *Value,
+ IN UINT32 CompareValue,

+ IN UINT32 ExchangeVal= ue

+ )

+=7B

+ UINT32 RetValue;<= /div>
+

+ RetValue =3D AsmInternalSyncCompareExchan= ge32 (

+ Value,

+ CompareValue,

+ ExchangeValue

+ );

+

+ retur= n RetValue;

+=7D

+

+/**
+ Performs an atomic compare exchange operation on a 64-bit unsign= ed integer.

+

+ Performs an atomic compare ex= change operation on the 64-bit unsigned integer specified

+= by Value. If Value is equal to CompareValue, then Value is set to Exchan= geValue and

+ CompareValue is returned. If Value is not equ= al to CompareValue, then Value is returned.

+ The compare e= xchange operation must be performed using MP safe mechanisms.

+

+ =40param=5Bin=5D Value A pointer to the 64-bit value= for the compare exchange

+ operation.

+ =40p= aram=5Bin=5D CompareValue 64-bit value used in compare operation.
+ =40param=5Bin=5D ExchangeValue 64-bit value used in exchange ope= ration.

+

+ =40return The original *Value bef= ore exchange.

+

+**/

+UINT64
+E=46IAPI

+InternalSyncCompareExchange64 (
+ IN volatile UINT64 *Value,

+ IN UINT64 CompareV= alue,

+ IN UINT64 ExchangeValue

+ )

=
+=7B

+ UINT64 RetValue;

+

= + RetValue =3D AsmInternalSyncCompareExchange64 (

+ Value,<= /div>
+ CompareValue,

+ ExchangeValue

+ );

+

+ return RetValue;

+=7D=

+

+/**

+ Performs an atomic in= crement of an 32-bit unsigned integer.

+

+ Pe= rforms an atomic increment of the 32-bit unsigned integer specified by
+ Value and returns the incremented value. The increment oper= ation must be

+ performed using MP safe mechanisms. The sta= te of the return value is not

+ guaranteed to be MP safe.
+

+ =40param=5Bin=5D Value A pointer to the 32= -bit value to increment.

+

+ =40return The in= cremented value.

+

+**/

+UINT32=

+E=46IAPI

+InternalSyncIncrement (

=
+ IN volatile UINT32 *Value

+ )

+=7B
+ return AsmInternalSyncIncrement (Value);

+=7D<= /div>
+

+/**

+ Performs an atomic dec= rement of an 32-bit unsigned integer.

+

+ Per= forms an atomic decrement of the 32-bit unsigned integer specified by
+ Value and returns the decrement value. The decrement operati= on must be

+ performed using MP safe mechanisms. The state = of the return value is not

+ guaranteed to be MP safe.
+

+ =40param=5Bin=5D Value A pointer to the 32-bi= t value to decrement.

+

+ =40return The decre= ment value.

+

+**/

+UINT32
+E=46IAPI

+InternalSyncDecrement (

= + IN volatile UINT32 *Value

+ )

+=7B
+ return AsmInternalSyncDecrement (Value);

+=7D
=
--
2.27.0
3D=22Sent --6332de25_66b4baed_19e08--