From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.132.183.28; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E560A2115993B for ; Thu, 27 Sep 2018 08:21:36 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A4DCF2DE3B; Thu, 27 Sep 2018 15:21:35 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-187.rdu2.redhat.com [10.10.120.187]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6BE1265323; Thu, 27 Sep 2018 15:21:34 +0000 (UTC) From: Laszlo Ersek To: =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , edk2-devel@lists.01.org Cc: Chao Zhang , michael.d.kinney@intel.com, Paolo Bonzini References: <9d023afc-13c9-d0a2-5bb4-dd889349f8ed@redhat.com> Message-ID: <1a8997d5-3345-a6f5-8d16-939aad50b043@redhat.com> Date: Thu, 27 Sep 2018 17:21:33 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <9d023afc-13c9-d0a2-5bb4-dd889349f8ed@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Thu, 27 Sep 2018 15:21:35 +0000 (UTC) Subject: Re: TCG MOR and processor caches X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Sep 2018 15:21:37 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit On 09/27/18 13:45, Laszlo Ersek wrote: > On 09/27/18 12:59, Marc-André Lureau wrote: >> Hi, >> >> According to "TCG Platform Reset Attack Mitigation Specification", if >> MOR bit is set, "it must initiate a vendor-specific method that >> overwrites all of system memory and the processor caches" >> >> In QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c and >> QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c, there is some >> code to clear RAM, however I don't see code that would clear the >> processor caches. >> >> For edk2/qemu, Paolo suggested it may be simpler to clear the cache >> unconditionally. How would you implement that? Using >> EFI_CPU_ARCH_PROTOCOL.FlushDataCache? (or direct AsmWbinvd call) > > I would call the appropriate low-level BaseLib.h function somewhere in > OvmfPkg/PlatformPei (unconditionally, yes). I haven't looked into > AsmWbinvd(), but if that's the right function, call that. (Checking the > Intel SDM re: WBINVD, I agree it could be the right one.) BTW: I assume the caches should be flushed on all logical processors; is that correct? If so, then EFI_PEI_MP_SERVICES_PPI will be needed, to run AsmWbinvd() on all processors. Luckily, OvmfPkg/PlatformPei already uses that service; see "OvmfPkg/PlatformPei/FeatureControl.c". Thanks Laszlo