There is a low probability that the XhciDxe will ASSERT

There is a low probability that the XhciDxe will ASSERT

[lurenjianullptr]

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Hi all,


Please check the Xhci log below. There's a low probability that the Xhci module will assert during a machine startup.


[20220210_16:41:22:796]        UsbHcGetHostAddrForPciAddr-forloop: Block->Buf = 0xF8B4C000, Block->BufLen = 0x10000
[20220210_16:41:22:796]UsbHcGetHostAddrForPciAddr: Enters with Mem = 0xF8B4FFD0, Size = 0x10
[20220210_16:41:22:807]        UsbHcGetHostAddrForPciAddr-forloop: Block->Buf = 0xF8B4C000, Block->BufLen = 0x10000
[20220210_16:41:22:807]UsbHcGetHostAddrForPciAddr: Enters with Mem = 0xF8B4FFE0, Size = 0x10
[20220210_16:41:22:816]        UsbHcGetHostAddrForPciAddr-forloop: Block->Buf = 0xF8B4C000, Block->BufLen = 0x10000
[20220210_16:41:22:848]UsbHcGetHostAddrForPciAddr: Enters with Mem = 0xF8B4FFF0, Size = 0x10
[20220210_16:41:22:849]        UsbHcGetHostAddrForPciAddr-forloop: Block->Buf = 0xF8B4C000, Block->BufLen = 0x10000
[20220210_16:41:23:314]Stop Slot = 1,Dci = 1
[20220210_16:41:23:314]XhcStopEndpoint: Slot = 0x1, Dci = 0x1
[20220210_16:41:23:322]UsbHcGetHostAddrForPciAddr: Enters with Mem = 0xF8B40000, Size = 0x10
[20220210_16:41:23:322]        UsbHcGetHostAddrForPciAddr-forloop: Block->Buf = 0xF8B4C000, Block->BufLen = 0x10000
[20220210_16:41:23:359]ASSERT [XhciDxe] /home/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c(306): (Block != ((void *) 0))


An expert think the issue is that one/more allocated transfer ring for a endpoint crosses the 64K-byte boundary.


When the TRB consumption in the transfer ring is about to cross the 64K-byte boundary (address 0xF8B4FFF0), the timeout happens.
And the expected subsequent TRB consumption should be address 0xF8B50000, but instead address 0xF8B40000 is returned from the Event Ring.


Since in the XHCI spec, it mentions in Section 4.9 that:
TRB Rings may be larger than a Page, however they shall not cross a 64K byte boundary. Refer to section 4.11.5.1 for more information on TRB Rings and page boundaries.

The expert’s suggestion is that somebody can help to add logic (maybe in UsbHcAllocateMem()) to ensure that the allocated memory for TRB Rings will not cross 64K-byte boundary. 


I'm not familiar with XHCI Spec and don't know how to solve it. 


I want to report the issue first and hope somebody can help me.



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