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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yeoreum.yun@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Mh43613qqgxOAjaodtbWHLEIx7686176AA= Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=KfPvqLon; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Hi Sahil! On 16/11/2023 11:45, sahil via groups.io wrote: > Add NOR flash DXE driver, this brings up NV storage on > QSPI's flash device using FVB protocol. > > Signed-off-by: sahil > --- > Platform/ARM/N1Sdp/N1SdpPlatform.dec | 5 +- > Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf | 72 ++ > Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h | 33 + > Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h | 491 +++= ++++++ > Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c | 409 +++= +++++ > Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c | 1100 +++= +++++++++++++++++ > Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c | 647 +++= +++++++++ > 7 files changed, 2756 insertions(+), 1 deletion(-) > > diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1= SdpPlatform.dec > index 16937197b8e8..67b5f4c871b6 100644 > --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec > +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec > @@ -1,7 +1,7 @@ > ## @file > # Describes the N1Sdp configuration. > # > -# Copyright (c) 2021, ARM Limited. All rights reserved.
> +# Copyright (c) 2021-2023, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > ## > @@ -89,3 +89,6 @@ > # unmapped reserved region results in a DECERR response. > # > gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049 > + > + # Base address of Cadence QSPI controller configuration registers > + gArmN1SdpTokenSpaceGuid.PcdCadenceQspiDxeRegBaseAddress|0x1C0C0000|UIN= T32|0x0000004A > diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf= b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf > new file mode 100644 > index 000000000000..62a4944c95db > --- /dev/null > +++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf > @@ -0,0 +1,72 @@ > +## @file > +# NOR flash DXE > +# > +# Copyright (c) 2023, ARM Limited. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x0001001B > + BASE_NAME =3D CadenceQspiDxe > + FILE_GUID =3D CC8A9713-4442-4A6C-B389-8B46490A064= 1 > + MODULE_TYPE =3D DXE_RUNTIME_DRIVER > + VERSION_STRING =3D 0.1 > + ENTRY_POINT =3D NorFlashInitialise > + > +[Sources] > + CadenceQspiDxe.c > + CadenceQspiReg.h > + NorFlash.c > + NorFlash.h > + NorFlashFvb.c > + > +[Packages] > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Platform/ARM/ARM.dec > + Platform/ARM/N1Sdp/N1SdpPlatform.dec > + > +[LibraryClasses] > + BaseLib > + BaseMemoryLib > + DebugLib > + DevicePathLib > + DxeServicesTableLib > + HobLib > + IoLib > + MemoryAllocationLib > + NorFlashInfoLib > + NorFlashPlatformLib > + TimerLib > + UefiBootServicesTableLib > + UefiDriverEntryPoint > + UefiLib > + UefiRuntimeLib > + UefiRuntimeServicesTableLib > + > +[Guids] > + gEdkiiNvVarStoreFormattedGuid > + gEfiAuthenticatedVariableGuid > + gEfiEventVirtualAddressChangeGuid > + gEfiSystemNvDataFvGuid > + gEfiVariableGuid > + gEfiGlobalVariableGuid > + > +[Protocols] > + gEfiDevicePathProtocolGuid > + gEfiFirmwareVolumeBlockProtocolGuid > + > +[FixedPcd] > + gArmN1SdpTokenSpaceGuid.PcdCadenceQspiDxeRegBaseAddress > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > + > +[Depex] > + gEfiCpuArchProtocolGuid > diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h b= /Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h > new file mode 100644 > index 000000000000..535e6d738d31 > --- /dev/null > +++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h > @@ -0,0 +1,33 @@ > +/** @file > + > + Copyright (c) 2023, ARM Limited. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef CADENCE_QSPI_REG_H_ > +#define CADENCE_QSPI_REG_H_ If you don't mind, would you add some of Reference page to understand NorFlash in CadenceQspi please with @par? > +/** > + Write a full block to given location. > + > + @param[in] Instance NOR flash Instance of variable store = region. > + @param[in] Lba The logical block address in NOR flas= h. > + @param[in] DataBuffer The data to write into NOR flash loca= tion. > + @param[in] BlockSizeInWords The number of bytes to write. > + > + @retval EFI_SUCCESS The write is completed. > +**/ > +STATIC > +EFI_STATUS > +NorFlashWriteFullBlock ( > + IN NOR_FLASH_INSTANCE *Instance, > + IN EFI_LBA Lba, > + IN UINT32 *DataBuffer, > + IN UINT32 BlockSizeInWords > + ) > +{ > + EFI_STATUS Status; > + UINTN WordAddress; > + UINT32 WordIndex; > + UINTN BlockAddress; > + NOR_FLASH_LOCK_CONTEXT Lock; > + > + Status =3D EFI_SUCCESS; > + > + // Get the physical address of the block > + BlockAddress =3D GET_NOR_BLOCK_ADDRESS ( > + Instance->RegionBaseAddress, > + Lba, > + BlockSizeInWords * 4 > + ); > + > + // Start writing from the first address at the start of the block > + WordAddress =3D BlockAddress; > + > + NorFlashLock (&Lock); > + > + Status =3D NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress); > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single b= lock at 0x%X\n", > + BlockAddress > + )); > + goto EXIT; > + } > + > + for (WordIndex =3D 0; > + WordIndex < BlockSizeInWords; > + WordIndex++, DataBuffer++, WordAddress +=3D 4) > + { > + Status =3D NorFlashWriteSingleWord (Instance, WordAddress, *DataBuff= er); > + if (EFI_ERROR (Status)) { > + goto EXIT; > + } > + } > + > +EXIT: > + NorFlashUnlock (&Lock); > + IIUC, NorFlashUnlockAndEraseSingleBlock calls NorFlashLock and NorFLashUnlock too. After calling NorFlashUnlock, it seems TPL or Interrupt seems to be enabled again. Isn't it problem? Thanks. -------- Sincerely, Levi. IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. If you are not the intended recipient, p= lease notify the sender immediately and do not disclose the contents to any= other person, use it for any purpose, or store or copy the information in = any medium. Thank you. -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112389): https://edk2.groups.io/g/devel/message/112389 Mute This Topic: https://groups.io/mt/102625036/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-