From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web12.7226.1646227952775237843 for ; Wed, 02 Mar 2022 05:32:32 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=cx5HQEOp; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: sebastien.boeuf@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646227952; x=1677763952; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=so3D+cz2C7PkBd63DJ/86iYg9YAjaFuXTravm9e1Pwk=; b=cx5HQEOpyC3ZEPZ33ga2ECAMLaIVH6rM+bHVIbARQaX0Dx284RUPW4mK VxSiW9wD4CPgtV80tuIDmrFFF+azK7CDI/NIO59VMYX3c3Gdm7JNkZuVA qV3o/52J7aQaD1i1T6kmDqPH8DlZCMw7xdHTODp2Bcxo9cWOs2pKg/7TE +e3yjKHuJS+BCfVr1idvDdrLmuXBdIbDjq5ssV3PgvRkRWqea9+hSjMDp nW6Dx5s0ppwz1U1RiJFuNP1cxdRU+iTQ41iY2CQbeJyRy4Rq4pWmfvF93 toJuuWGtj/AmnILcvTKXPz+vi4v1+dduNr7JFFzBqaenFYDZAv6mIV0RC g==; X-IronPort-AV: E=McAfee;i="6200,9189,10273"; a="250974756" X-IronPort-AV: E=Sophos;i="5.90,149,1643702400"; d="scan'208";a="250974756" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2022 05:32:25 -0800 X-IronPort-AV: E=Sophos;i="5.90,149,1643702400"; d="scan'208";a="535389387" Received: from spearce-mobl1.amr.corp.intel.com (HELO sboeuf-mobl.home) ([10.252.27.130]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2022 05:32:24 -0800 From: "Boeuf, Sebastien" To: devel@edk2.groups.io Cc: jiewen.yao@intel.com, jordan.l.justen@intel.com, kraxel@redhat.com, sebastien.boeuf@intel.com Subject: [PATCH v6 5/8] OvmfPkg: Generate CloudHv as a PVH ELF binary Date: Wed, 2 Mar 2022 14:31:34 +0100 Message-Id: <1f82cc46921762b209436aff32d6b098e4a3ea27.1646227817.git.sebastien.boeuf@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable From: Sebastien Boeuf Following the model from the Xen target, CloudHv is generated as a PVH ELF binary to take advantage of the PVH specification, which requires less emulation from the VMM. The fdf include file CloudHvElfHeader.fdf.inc has been generated from the following commands: $ gcc -D PVH64 -o elf_gen OvmfPkg/OvmfXenElfHeaderGenerator.c $ ./elf_gen 4194304 OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc Signed-off-by: Sebastien Boeuf --- OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc | 54 ++++++++++++++++++++++++ OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/CloudHv/CloudHvX64.fdf | 15 +++++-- 3 files changed, 66 insertions(+), 5 deletions(-) create mode 100644 OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc diff --git a/OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc b/OvmfPkg/CloudHv/Clo= udHvElfHeader.fdf.inc new file mode 100644 index 0000000000..8377e30bdc --- /dev/null +++ b/OvmfPkg/CloudHv/CloudHvElfHeader.fdf.inc @@ -0,0 +1,54 @@ +## @file +# FDF include file that defines a PVH ELF header. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +DATA =3D { + # ELF file header + 0x7f, 0x45, 0x4c, 0x46, 0x02, 0x01, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, + 0xd0, 0xff, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, # hdr.e_entry + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x38, 0x00, 0x0= 2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + # ELF Program segment headers + # - Load segment + 0x01, 0x00, 0x00, 0x00, + 0x07, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + # - ELFNOTE segment + 0x04, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0xb0, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xb0, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xb0, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + # XEN_ELFNOTE_PHYS32_ENTRY + 0x04, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, + 0x12, 0x00, 0x00, 0x00, + 0x58, 0x65, 0x6e, 0x00, + 0xd0, 0xff, 0x4f, 0x00 +} diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index 3172100310..b4d855d80f 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -631,7 +631,7 @@ # ##########################################################################= ###### [Components] - OvmfPkg/ResetVector/ResetVector.inf + OvmfPkg/XenResetVector/XenResetVector.inf = # # SEC Phase modules diff --git a/OvmfPkg/CloudHv/CloudHvX64.fdf b/OvmfPkg/CloudHv/CloudHvX64.fdf index 0974e76ac8..282bcf8634 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.fdf +++ b/OvmfPkg/CloudHv/CloudHvX64.fdf @@ -14,8 +14,8 @@ !include OvmfPkg/OvmfPkgDefines.fdf.inc = # -# Build the variable store and the firmware code as one unified flash devi= ce -# image. +# This will allow the flash device image to be recognize as an ELF, with f= irst +# an ELF headers, then the firmware code. # [FD.CLOUDHV] BaseAddress =3D $(FW_BASE_ADDRESS) @@ -24,7 +24,14 @@ ErasePolarity =3D 1 BlockSize =3D $(BLOCK_SIZE) NumBlocks =3D $(FW_BLOCKS) = -0x00000000|$(FVMAIN_SIZE) +# +# Leaving 4kiB for the PVH ELF header. This is more than enough. +# +0x00000000|0x00001000 + +!include CloudHvElfHeader.fdf.inc + +0x00001000|$(FVMAIN_SIZE) FV =3D FVMAIN_COMPACT = $(SECFV_OFFSET)|$(SECFV_SIZE) @@ -114,7 +121,7 @@ READ_LOCK_STATUS =3D TRUE # INF OvmfPkg/Sec/SecMain.inf = -INF RuleOverride=3DRESET_VECTOR OvmfPkg/ResetVector/ResetVector.inf +INF RuleOverride=3DRESET_VECTOR OvmfPkg/XenResetVector/XenResetVector.inf = ##########################################################################= ###### [FV.PEIFV] -- = 2.32.0 --------------------------------------------------------------------- Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, = 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. NANTERRE Capital: 4,572,000 Euros This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.