From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B5B8D1A1E76 for ; Tue, 6 Sep 2016 04:39:40 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP; 06 Sep 2016 04:39:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,291,1470726000"; d="scan'208";a="5490840" Received: from jfan12-desk.ccr.corp.intel.com ([10.239.9.5]) by orsmga004.jf.intel.com with ESMTP; 06 Sep 2016 04:39:17 -0700 From: Jeff Fan To: edk2-devel@lists.01.org Cc: Michael Kinney , Feng Tian , Giri P Mudusuru Date: Tue, 6 Sep 2016 19:38:45 +0800 Message-Id: <20160906113852.11408-14-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20160906113852.11408-1-jeff.fan@intel.com> References: <20160906113852.11408-1-jeff.fan@intel.com> Subject: [Patch 13/20] UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Sep 2016 11:39:40 -0000 Cc: Michael Kinney Cc: Feng Tian Cc: Giri P Mudusuru Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h index a8916b4..62c5b7e 100644 --- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h @@ -40,6 +40,7 @@ Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR); AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr); @endcode + @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM. **/ #define MSR_PENTIUM_P5_MC_ADDR 0x00000000 @@ -58,6 +59,7 @@ Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE); AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr); @endcode + @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM. **/ #define MSR_PENTIUM_P5_MC_TYPE 0x00000001 @@ -76,6 +78,7 @@ Msr = AsmReadMsr64 (MSR_PENTIUM_TSC); AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr); @endcode + @note MSR_PENTIUM_TSC is defined as TSC in SDM. **/ #define MSR_PENTIUM_TSC 0x00000010 @@ -94,6 +97,7 @@ Msr = AsmReadMsr64 (MSR_PENTIUM_CESR); AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr); @endcode + @note MSR_PENTIUM_CESR is defined as CESR in SDM. **/ #define MSR_PENTIUM_CESR 0x00000011 @@ -112,6 +116,8 @@ Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0); AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr); @endcode + @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM. + MSR_PENTIUM_CTR1 is defined as CTR1 in SDM. @{ **/ #define MSR_PENTIUM_CTR0 0x00000012 -- 2.9.3.windows.2