From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8DF581A1E53 for ; Tue, 6 Sep 2016 04:39:42 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP; 06 Sep 2016 04:39:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,291,1470726000"; d="scan'208";a="5490880" Received: from jfan12-desk.ccr.corp.intel.com ([10.239.9.5]) by orsmga004.jf.intel.com with ESMTP; 06 Sep 2016 04:39:24 -0700 From: Jeff Fan To: edk2-devel@lists.01.org Cc: Michael Kinney , Feng Tian , Giri P Mudusuru Date: Tue, 6 Sep 2016 19:38:49 +0800 Message-Id: <20160906113852.11408-18-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20160906113852.11408-1-jeff.fan@intel.com> References: <20160906113852.11408-1-jeff.fan@intel.com> Subject: [Patch 17/20] UefiCpuPkg/Xeon5600Msr.h: add MSR reference from SDM in comment X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Sep 2016 11:39:42 -0000 Cc: Michael Kinney Cc: Feng Tian Cc: Giri P Mudusuru Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h index a4c6ba0..504c76b 100644 --- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h +++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h @@ -43,6 +43,7 @@ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG); AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64); @endcode + @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. **/ #define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C @@ -92,6 +93,7 @@ typedef union { Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1); AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr); @endcode + @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. **/ #define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7 @@ -112,6 +114,7 @@ typedef union { Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT); @endcode + @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. **/ #define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD @@ -176,6 +179,7 @@ typedef union { Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS); AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr); @endcode + @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM. **/ #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0 -- 2.9.3.windows.2