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From: Jeff Fan <jeff.fan@intel.com>
To: edk2-devel@lists.01.org
Cc: Michael Kinney <michael.d.kinney@intel.com>,
	Feng Tian <feng.tian@intel.com>,
	Giri P Mudusuru <giri.p.mudusuru@intel.com>
Subject: [Patch 19/20] UefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in comment
Date: Tue,  6 Sep 2016 19:38:51 +0800	[thread overview]
Message-ID: <20160906113852.11408-20-jeff.fan@intel.com> (raw)
In-Reply-To: <20160906113852.11408-1-jeff.fan@intel.com>

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 31 +++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
index b95f963..3128c4b 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
   AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
   @endcode
+  @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40
 
@@ -76,6 +78,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41
 
@@ -94,6 +97,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42
 
@@ -112,6 +116,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
   @{
 **/
 #define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50
@@ -137,6 +147,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
   @endcode
+  @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
   @{
 **/
 #define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51
@@ -162,6 +178,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0
 
@@ -180,6 +197,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1
 
@@ -198,6 +216,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2
 
@@ -216,6 +235,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
   @{
 **/
 #define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0
@@ -241,6 +266,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
   @endcode
+  @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
   @{
 **/
 #define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1
-- 
2.9.3.windows.2



  parent reply	other threads:[~2016-09-06 11:39 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
2016-09-06 11:38 ` [Patch 01/20] UefiCpuPkg/ArchitecturalMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 02/20] UefiCpuPkg/AtomMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 03/20] UefiCpuPkg/BroadwellMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 04/20] UefiCpuPkg/Core2Msr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 05/20] UefiCpuPkg/CoreMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 06/20] UefiCpuPkg/HaswellEMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 07/20] UefiCpuPkg/HaswellMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 08/20] UefiCpuPkg/IvyBridgeMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 09/20] UefiCpuPkg/NehalemMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 10/20] UefiCpuPkg/P6Msr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 11/20] UefiCpuPkg/Pentium4Msr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 12/20] UefiCpuPkg/PentiumMMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 13/20] UefiCpuPkg/PentiumMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 14/20] UefiCpuPkg/SandyBridgeMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 15/20] UefiCpuPkg/SilvermontMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 16/20] UefiCpuPkg/SkylakeMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 17/20] UefiCpuPkg/Xeon5600Msr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 18/20] UefiCpuPkg/XeonDMsr.h: " Jeff Fan
2016-09-06 11:38 ` Jeff Fan [this message]
2016-09-06 11:38 ` [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: " Jeff Fan
2016-09-06 17:27   ` Mudusuru, Giri P

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