From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 310451A1E4D for ; Tue, 6 Sep 2016 04:39:43 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP; 06 Sep 2016 04:39:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,291,1470726000"; d="scan'208";a="5490899" Received: from jfan12-desk.ccr.corp.intel.com ([10.239.9.5]) by orsmga004.jf.intel.com with ESMTP; 06 Sep 2016 04:39:27 -0700 From: Jeff Fan To: edk2-devel@lists.01.org Cc: Michael Kinney , Feng Tian , Giri P Mudusuru Date: Tue, 6 Sep 2016 19:38:51 +0800 Message-Id: <20160906113852.11408-20-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20160906113852.11408-1-jeff.fan@intel.com> References: <20160906113852.11408-1-jeff.fan@intel.com> Subject: [Patch 19/20] UefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in comment X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Sep 2016 11:39:43 -0000 Cc: Michael Kinney Cc: Feng Tian Cc: Giri P Mudusuru Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 31 +++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h index b95f963..3128c4b 100644 --- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h +++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h @@ -40,6 +40,7 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT); AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr); @endcode + @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. **/ #define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD @@ -58,6 +59,7 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL); AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr); @endcode + @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM. **/ #define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40 @@ -76,6 +78,7 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS); AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr); @endcode + @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM. **/ #define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41 @@ -94,6 +97,7 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL); AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr); @endcode + @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM. **/ #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42 @@ -112,6 +116,12 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0); AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr); @endcode + @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM. + MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM. + MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM. + MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM. + MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM. + MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM. @{ **/ #define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50 @@ -137,6 +147,12 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0); AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr); @endcode + @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM. + MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM. + MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM. + MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM. + MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM. + MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM. @{ **/ #define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51 @@ -162,6 +178,7 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL); AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr); @endcode + @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM. **/ #define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0 @@ -180,6 +197,7 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS); AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr); @endcode + @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM. **/ #define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1 @@ -198,6 +216,7 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL); AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr); @endcode + @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM. **/ #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2 @@ -216,6 +235,12 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0); AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr); @endcode + @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM. + MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM. + MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM. + MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM. + MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM. + MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM. @{ **/ #define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0 @@ -241,6 +266,12 @@ Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0); AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr); @endcode + @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM. + MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM. + MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM. + MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM. + MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM. + MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM. @{ **/ #define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1 -- 2.9.3.windows.2