[Patch 00/20] add MSR reference from SDM in comment

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* [Patch 00/20] add MSR reference from SDM in comment
@ 2016-09-06 11:38 Jeff Fan
  2016-09-06 11:38 ` [Patch 01/20] UefiCpuPkg/ArchitecturalMsr.h: " Jeff Fan
                   ` (19 more replies)
  0 siblings, 20 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel

Added original MSRs reference in SDM in comments. It is used to help
searching MSR definitions.

Jeff Fan (20):
  UefiCpuPkg/ArchitecturalMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/AtomMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/BroadwellMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/Core2Msr.h: add MSR reference from SDM in comment
  UefiCpuPkg/CoreMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/HaswellEMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/HaswellMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/NehalemMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/P6Msr.h: add MSR reference from SDM in comment
  UefiCpuPkg/Pentium4Msr.h: add MSR reference from SDM in comment
  UefiCpuPkg/PentiumMMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/SandyBridgeMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/SilvermontMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/SkylakeMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/Xeon5600Msr.h: add MSR reference from SDM in comment
  UefiCpuPkg/XeonDMsr.h: add MSR reference from SDM in comment
  UefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in comment
  UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment

 UefiCpuPkg/Include/Register/ArchitecturalMsr.h   | 352 +++++++++++++++++
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h        |  37 ++
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h   |   3 +
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h       |  52 +++
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h        |  58 +++
 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h    | 360 ++++++++++++++++++
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h     |  58 +++
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h   | 218 +++++++++++
 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h     | 465 +++++++++++++++++++++++
 UefiCpuPkg/Include/Register/Msr/P6Msr.h          |  83 ++++
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h    | 167 ++++++++
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h    |  25 ++
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h     |   6 +
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 271 +++++++++++++
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h  |  57 +++
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h     |  83 ++++
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h    |   4 +
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h       | 106 ++++++
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h      |  31 ++
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h     |  51 +++
 20 files changed, 2487 insertions(+)

-- 
2.9.3.windows.2



^ permalink raw reply	[flat|nested] 22+ messages in thread

* [Patch 01/20] UefiCpuPkg/ArchitecturalMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 02/20] UefiCpuPkg/AtomMsr.h: " Jeff Fan
                   ` (18 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 352 +++++++++++++++++++++++++
 1 file changed, 352 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 4d4ade4..7de1c4b 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -38,6 +38,7 @@
   Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
 **/
 #define MSR_IA32_P5_MC_ADDR                      0x00000000
 
@@ -56,6 +57,7 @@
   Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
 **/
 #define MSR_IA32_P5_MC_TYPE                      0x00000001
 
@@ -75,6 +77,7 @@
   Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
   AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
   @endcode
+  @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
 **/
 #define MSR_IA32_MONITOR_FILTER_SIZE             0x00000006
 
@@ -94,6 +97,7 @@
   Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
   AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
   @endcode
+  @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
 **/
 #define MSR_IA32_TIME_STAMP_COUNTER              0x00000010
 
@@ -115,6 +119,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
   @endcode
+  @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
 **/
 #define MSR_IA32_PLATFORM_ID                     0x00000017
 
@@ -168,6 +173,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
   AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
   @endcode
+  @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
 **/
 #define MSR_IA32_APIC_BASE                       0x0000001B
 
@@ -227,6 +233,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
   AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
 **/
 #define MSR_IA32_FEATURE_CONTROL                 0x0000003A
 
@@ -326,6 +333,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
   AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
   @endcode
+  @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
 **/
 #define MSR_IA32_TSC_ADJUST                      0x0000003B
 
@@ -348,6 +356,7 @@ typedef union {
   Msr = 0;
   AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
   @endcode
+  @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
 **/
 #define MSR_IA32_BIOS_UPDT_TRIG                  0x00000079
 
@@ -370,6 +379,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
   @endcode
+  @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
 **/
 #define MSR_IA32_BIOS_SIGN_ID                    0x0000008B
 
@@ -417,6 +427,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
   AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
 **/
 #define MSR_IA32_SMM_MONITOR_CTL                 0x0000009B
 
@@ -475,6 +486,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
   @endcode
+  @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
 **/
 #define MSR_IA32_SMBASE                          0x0000009E
 
@@ -494,6 +506,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_PMC0);
   AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
   @endcode
+  @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
+        MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
+        MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
+        MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
+        MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
+        MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
+        MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
+        MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
   @{
 **/
 #define MSR_IA32_PMC0                            0x000000C1
@@ -524,6 +544,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MPERF);
   AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
   @endcode
+  @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
 **/
 #define MSR_IA32_MPERF                           0x000000E7
 
@@ -545,6 +566,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_APERF);
   AsmWriteMsr64 (MSR_IA32_APERF, Msr);
   @endcode
+  @note MSR_IA32_APERF is defined as IA32_APERF in SDM.
 **/
 #define MSR_IA32_APERF                           0x000000E8
 
@@ -565,6 +587,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
   @endcode
+  @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
 **/
 #define MSR_IA32_MTRRCAP                         0x000000FE
 
@@ -624,6 +647,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
   AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
   @endcode
+  @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
 **/
 #define MSR_IA32_SYSENTER_CS                     0x00000174
 
@@ -667,6 +691,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
   AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
   @endcode
+  @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
 **/
 #define MSR_IA32_SYSENTER_ESP                    0x00000175
 
@@ -685,6 +710,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
   AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
   @endcode
+  @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
 **/
 #define MSR_IA32_SYSENTER_EIP                    0x00000176
 
@@ -705,6 +731,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
   @endcode
+  @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
 **/
 #define MSR_IA32_MCG_CAP                         0x00000179
 
@@ -798,6 +825,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
   AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
 **/
 #define MSR_IA32_MCG_STATUS                      0x0000017A
 
@@ -856,6 +884,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
   AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
   @endcode
+  @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
 **/
 #define MSR_IA32_MCG_CTL                         0x0000017B
 
@@ -876,6 +905,10 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
+        MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
+        MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
+        MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
   @{
 **/
 #define MSR_IA32_PERFEVTSEL0                     0x00000186
@@ -974,6 +1007,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
   @endcode
+  @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
 **/
 #define MSR_IA32_PERF_STATUS                     0x00000198
 
@@ -1019,6 +1053,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
   AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
 **/
 #define MSR_IA32_PERF_CTL                        0x00000199
 
@@ -1066,6 +1101,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
   AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
   @endcode
+  @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
 **/
 #define MSR_IA32_CLOCK_MODULATION                0x0000019A
 
@@ -1124,6 +1160,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
   AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
   @endcode
+  @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
 **/
 #define MSR_IA32_THERM_INTERRUPT                 0x0000019B
 
@@ -1208,6 +1245,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
   @endcode
+  @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
 **/
 #define MSR_IA32_THERM_STATUS                    0x0000019C
 
@@ -1327,6 +1365,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_IA32_MISC_ENABLE                     0x000001A0
 
@@ -1456,6 +1495,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
   AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
   @endcode
+  @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
 **/
 #define MSR_IA32_ENERGY_PERF_BIAS                0x000001B0
 
@@ -1503,6 +1543,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
   @endcode
+  @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
 **/
 #define MSR_IA32_PACKAGE_THERM_STATUS            0x000001B1
 
@@ -1600,6 +1641,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
   AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
 **/
 #define MSR_IA32_PACKAGE_THERM_INTERRUPT         0x000001B2
 
@@ -1680,6 +1722,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
   AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
 **/
 #define MSR_IA32_DEBUGCTL                        0x000001D9
 
@@ -1790,6 +1833,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
   AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
   @endcode
+  @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
 **/
 #define MSR_IA32_SMRR_PHYSBASE                   0x000001F2
 
@@ -1840,6 +1884,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
   AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
   @endcode
+  @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
 **/
 #define MSR_IA32_SMRR_PHYSMASK                   0x000001F3
 
@@ -1886,6 +1931,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
   @endcode
+  @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
 **/
 #define MSR_IA32_PLATFORM_DCA_CAP                0x000001F8
 
@@ -1904,6 +1950,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
   AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
   @endcode
+  @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
 **/
 #define MSR_IA32_CPU_DCA_CAP                     0x000001F9
 
@@ -1924,6 +1971,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
   AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
   @endcode
+  @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
 **/
 #define MSR_IA32_DCA_0_CAP                       0x000001FA
 
@@ -1999,6 +2047,16 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
   AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
   @endcode
+  @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.
+        MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.
+        MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.
+        MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.
+        MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.
+        MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.
+        MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.
+        MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.
+        MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.
+        MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
   @{
 **/
 #define MSR_IA32_MTRR_PHYSBASE0                  0x00000200
@@ -2065,6 +2123,16 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
   AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
   @endcode
+  @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.
+        MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.
+        MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.
+        MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.
+        MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.
+        MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.
+        MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.
+        MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.
+        MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.
+        MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
   @{
 **/
 #define MSR_IA32_MTRR_PHYSMASK0                  0x00000201
@@ -2128,6 +2196,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX64K_00000               0x00000250
 
@@ -2146,6 +2215,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX16K_80000               0x00000258
 
@@ -2164,6 +2234,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX16K_A0000               0x00000259
 
@@ -2182,6 +2253,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX4K_C0000                0x00000268
 
@@ -2200,6 +2272,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX4K_C8000                0x00000269
 
@@ -2218,6 +2291,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX4K_D0000                0x0000026A
 
@@ -2236,6 +2310,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX4K_D8000                0x0000026B
 
@@ -2254,6 +2329,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX4K_E0000                0x0000026C
 
@@ -2272,6 +2348,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX4K_E8000                0x0000026D
 
@@ -2290,6 +2367,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX4K_F0000                0x0000026E
 
@@ -2308,6 +2386,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
   AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
   @endcode
+  @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
 **/
 #define MSR_IA32_MTRR_FIX4K_F8000                0x0000026F
 
@@ -2328,6 +2407,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
   AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PAT is defined as IA32_PAT in SDM.
 **/
 #define MSR_IA32_PAT                             0x00000277
 
@@ -2404,6 +2484,38 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
   AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
   @endcode
+  @note MSR_IA32_MC0_CTL2  is defined as IA32_MC0_CTL2  in SDM.
+        MSR_IA32_MC1_CTL2  is defined as IA32_MC1_CTL2  in SDM.
+        MSR_IA32_MC2_CTL2  is defined as IA32_MC2_CTL2  in SDM.
+        MSR_IA32_MC3_CTL2  is defined as IA32_MC3_CTL2  in SDM.
+        MSR_IA32_MC4_CTL2  is defined as IA32_MC4_CTL2  in SDM.
+        MSR_IA32_MC5_CTL2  is defined as IA32_MC5_CTL2  in SDM.
+        MSR_IA32_MC6_CTL2  is defined as IA32_MC6_CTL2  in SDM.
+        MSR_IA32_MC7_CTL2  is defined as IA32_MC7_CTL2  in SDM.
+        MSR_IA32_MC8_CTL2  is defined as IA32_MC8_CTL2  in SDM.
+        MSR_IA32_MC9_CTL2  is defined as IA32_MC9_CTL2  in SDM.
+        MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.
+        MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.
+        MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.
+        MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.
+        MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.
+        MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.
+        MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.
+        MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.
+        MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.
+        MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.
+        MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.
+        MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.
+        MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.
+        MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.
+        MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.
+        MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.
+        MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.
+        MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.
+        MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.
+        MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.
+        MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.
+        MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
   @{
 **/
 #define MSR_IA32_MC0_CTL2                        0x00000280
@@ -2488,6 +2600,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
   AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
   @endcode
+  @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
 **/
 #define MSR_IA32_MTRR_DEF_TYPE                   0x000002FF
 
@@ -2541,6 +2654,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
   AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
   @endcode
+  @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
 **/
 #define MSR_IA32_FIXED_CTR0                      0x00000309
 
@@ -2560,6 +2674,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
   AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
   @endcode
+  @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
 **/
 #define MSR_IA32_FIXED_CTR1                      0x0000030A
 
@@ -2579,6 +2694,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
   AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
   @endcode
+  @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
 **/
 #define MSR_IA32_FIXED_CTR2                      0x0000030B
 
@@ -2599,6 +2715,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
   AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
 **/
 #define MSR_IA32_PERF_CAPABILITIES               0x00000345
 
@@ -2667,6 +2784,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
   AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
 **/
 #define MSR_IA32_FIXED_CTR_CTRL                  0x0000038D
 
@@ -2767,6 +2885,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
   @endcode
+  @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
 **/
 #define MSR_IA32_PERF_GLOBAL_STATUS              0x0000038E
 
@@ -2882,6 +3001,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
   AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
 **/
 #define MSR_IA32_PERF_GLOBAL_CTRL                0x0000038F
 
@@ -2930,6 +3050,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
   AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
 **/
 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL            0x00000390
 
@@ -2998,6 +3119,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
   AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
 **/
 #define MSR_IA32_PERF_GLOBAL_STATUS_RESET        0x00000390
 
@@ -3078,6 +3200,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
   AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
 **/
 #define MSR_IA32_PERF_GLOBAL_STATUS_SET          0x00000391
 
@@ -3152,6 +3275,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
   @endcode
+  @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
 **/
 #define MSR_IA32_PERF_GLOBAL_INUSE               0x00000392
 
@@ -3204,6 +3328,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
   AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
 **/
 #define MSR_IA32_PEBS_ENABLE                     0x000003F1
 
@@ -3252,6 +3377,35 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
   AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
   @endcode
+  @note MSR_IA32_MC0_CTL  is defined as IA32_MC0_CTL  in SDM.
+        MSR_IA32_MC1_CTL  is defined as IA32_MC1_CTL  in SDM.
+        MSR_IA32_MC2_CTL  is defined as IA32_MC2_CTL  in SDM.
+        MSR_IA32_MC3_CTL  is defined as IA32_MC3_CTL  in SDM.
+        MSR_IA32_MC4_CTL  is defined as IA32_MC4_CTL  in SDM.
+        MSR_IA32_MC5_CTL  is defined as IA32_MC5_CTL  in SDM.
+        MSR_IA32_MC6_CTL  is defined as IA32_MC6_CTL  in SDM.
+        MSR_IA32_MC7_CTL  is defined as IA32_MC7_CTL  in SDM.
+        MSR_IA32_MC8_CTL  is defined as IA32_MC8_CTL  in SDM.
+        MSR_IA32_MC9_CTL  is defined as IA32_MC9_CTL  in SDM.
+        MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.
+        MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.
+        MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.
+        MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.
+        MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.
+        MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.
+        MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.
+        MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.
+        MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.
+        MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.
+        MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.
+        MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.
+        MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.
+        MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.
+        MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.
+        MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.
+        MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.
+        MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.
+        MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
   @{
 **/
 #define MSR_IA32_MC0_CTL                         0x00000400
@@ -3300,6 +3454,35 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
   AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
   @endcode
+  @note MSR_IA32_MC0_STATUS  is defined as IA32_MC0_STATUS  in SDM.
+        MSR_IA32_MC1_STATUS  is defined as IA32_MC1_STATUS  in SDM.
+        MSR_IA32_MC2_STATUS  is defined as IA32_MC2_STATUS  in SDM.
+        MSR_IA32_MC3_STATUS  is defined as IA32_MC3_STATUS  in SDM.
+        MSR_IA32_MC4_STATUS  is defined as IA32_MC4_STATUS  in SDM.
+        MSR_IA32_MC5_STATUS  is defined as IA32_MC5_STATUS  in SDM.
+        MSR_IA32_MC6_STATUS  is defined as IA32_MC6_STATUS  in SDM.
+        MSR_IA32_MC7_STATUS  is defined as IA32_MC7_STATUS  in SDM.
+        MSR_IA32_MC8_STATUS  is defined as IA32_MC8_STATUS  in SDM.
+        MSR_IA32_MC9_STATUS  is defined as IA32_MC9_STATUS  in SDM.
+        MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.
+        MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.
+        MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.
+        MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.
+        MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.
+        MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.
+        MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.
+        MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.
+        MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.
+        MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.
+        MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.
+        MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.
+        MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.
+        MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.
+        MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.
+        MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.
+        MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.
+        MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.
+        MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
   @{
 **/
 #define MSR_IA32_MC0_STATUS                      0x00000401
@@ -3348,6 +3531,35 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
   AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
   @endcode
+  @note MSR_IA32_MC0_ADDR  is defined as IA32_MC0_ADDR  in SDM.
+        MSR_IA32_MC1_ADDR  is defined as IA32_MC1_ADDR  in SDM.
+        MSR_IA32_MC2_ADDR  is defined as IA32_MC2_ADDR  in SDM.
+        MSR_IA32_MC3_ADDR  is defined as IA32_MC3_ADDR  in SDM.
+        MSR_IA32_MC4_ADDR  is defined as IA32_MC4_ADDR  in SDM.
+        MSR_IA32_MC5_ADDR  is defined as IA32_MC5_ADDR  in SDM.
+        MSR_IA32_MC6_ADDR  is defined as IA32_MC6_ADDR  in SDM.
+        MSR_IA32_MC7_ADDR  is defined as IA32_MC7_ADDR  in SDM.
+        MSR_IA32_MC8_ADDR  is defined as IA32_MC8_ADDR  in SDM.
+        MSR_IA32_MC9_ADDR  is defined as IA32_MC9_ADDR  in SDM.
+        MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.
+        MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.
+        MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.
+        MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.
+        MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.
+        MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.
+        MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.
+        MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.
+        MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.
+        MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.
+        MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.
+        MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.
+        MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.
+        MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.
+        MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.
+        MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.
+        MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.
+        MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.
+        MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
   @{
 **/
 #define MSR_IA32_MC0_ADDR                        0x00000402
@@ -3396,6 +3608,35 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
   AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
   @endcode
+  @note MSR_IA32_MC0_MISC  is defined as IA32_MC0_MISC  in SDM.
+        MSR_IA32_MC1_MISC  is defined as IA32_MC1_MISC  in SDM.
+        MSR_IA32_MC2_MISC  is defined as IA32_MC2_MISC  in SDM.
+        MSR_IA32_MC3_MISC  is defined as IA32_MC3_MISC  in SDM.
+        MSR_IA32_MC4_MISC  is defined as IA32_MC4_MISC  in SDM.
+        MSR_IA32_MC5_MISC  is defined as IA32_MC5_MISC  in SDM.
+        MSR_IA32_MC6_MISC  is defined as IA32_MC6_MISC  in SDM.
+        MSR_IA32_MC7_MISC  is defined as IA32_MC7_MISC  in SDM.
+        MSR_IA32_MC8_MISC  is defined as IA32_MC8_MISC  in SDM.
+        MSR_IA32_MC9_MISC  is defined as IA32_MC9_MISC  in SDM.
+        MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.
+        MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.
+        MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.
+        MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.
+        MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.
+        MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.
+        MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.
+        MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.
+        MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.
+        MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.
+        MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.
+        MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.
+        MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.
+        MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.
+        MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.
+        MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.
+        MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.
+        MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.
+        MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
   @{
 **/
 #define MSR_IA32_MC0_MISC                        0x00000403
@@ -3444,6 +3685,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
   @endcode
+  @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
 **/
 #define MSR_IA32_VMX_BASIC                       0x00000480
 
@@ -3462,6 +3704,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
   @endcode
+  @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
 **/
 #define MSR_IA32_VMX_PINBASED_CTLS               0x00000481
 
@@ -3481,6 +3724,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
   @endcode
+  @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
 **/
 #define MSR_IA32_VMX_PROCBASED_CTLS              0x00000482
 
@@ -3499,6 +3743,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
   @endcode
+  @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
 **/
 #define MSR_IA32_VMX_EXIT_CTLS                   0x00000483
 
@@ -3517,6 +3762,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
   @endcode
+  @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
 **/
 #define MSR_IA32_VMX_ENTRY_CTLS                  0x00000484
 
@@ -3535,6 +3781,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_MISC);
   @endcode
+  @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
 **/
 #define MSR_IA32_VMX_MISC                        0x00000485
 
@@ -3553,6 +3800,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
   @endcode
+  @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
 **/
 #define MSR_IA32_VMX_CR0_FIXED0                  0x00000486
 
@@ -3571,6 +3819,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
   @endcode
+  @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
 **/
 #define MSR_IA32_VMX_CR0_FIXED1                  0x00000487
 
@@ -3589,6 +3838,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
   @endcode
+  @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
 **/
 #define MSR_IA32_VMX_CR4_FIXED0                  0x00000488
 
@@ -3607,6 +3857,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
   @endcode
+  @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
 **/
 #define MSR_IA32_VMX_CR4_FIXED1                  0x00000489
 
@@ -3625,6 +3876,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
   @endcode
+  @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
 **/
 #define MSR_IA32_VMX_VMCS_ENUM                   0x0000048A
 
@@ -3644,6 +3896,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
   @endcode
+  @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
 **/
 #define MSR_IA32_VMX_PROCBASED_CTLS2             0x0000048B
 
@@ -3663,6 +3916,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
   @endcode
+  @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
 **/
 #define MSR_IA32_VMX_EPT_VPID_CAP                0x0000048C
 
@@ -3682,6 +3936,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
   @endcode
+  @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
 **/
 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS          0x0000048D
 
@@ -3701,6 +3956,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
   @endcode
+  @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
 **/
 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS         0x0000048E
 
@@ -3719,6 +3975,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
   @endcode
+  @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
 **/
 #define MSR_IA32_VMX_TRUE_EXIT_CTLS              0x0000048F
 
@@ -3737,6 +3994,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
   @endcode
+  @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
 **/
 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS             0x00000490
 
@@ -3755,6 +4013,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
   @endcode
+  @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
 **/
 #define MSR_IA32_VMX_VMFUNC                      0x00000491
 
@@ -3774,6 +4033,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
   AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
   @endcode
+  @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.
+        MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.
+        MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.
+        MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.
+        MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.
+        MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.
+        MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.
+        MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
   @{
 **/
 #define MSR_IA32_A_PMC0                          0x000004C1
@@ -3803,6 +4070,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
   AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
 **/
 #define MSR_IA32_MCG_EXT_CTL                     0x000004D0
 
@@ -3848,6 +4116,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
   @endcode
+  @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
 **/
 #define MSR_IA32_SGX_SVN_STATUS                  0x00000500
 
@@ -3902,6 +4171,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
   AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
   @endcode
+  @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
 **/
 #define MSR_IA32_RTIT_OUTPUT_BASE                0x00000560
 
@@ -3948,6 +4218,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
   AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
   @endcode
+  @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
 **/
 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS           0x00000561
 
@@ -3992,6 +4263,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
   AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
 **/
 #define MSR_IA32_RTIT_CTL                        0x00000570
 
@@ -4105,6 +4377,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
   AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
 **/
 #define MSR_IA32_RTIT_STATUS                     0x00000571
 
@@ -4169,6 +4442,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
   AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
   @endcode
+  @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
 **/
 #define MSR_IA32_RTIT_CR3_MATCH                  0x00000572
 
@@ -4213,6 +4487,10 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
   AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
   @endcode
+  @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.
+        MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.
+        MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.
+        MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
   @{
 **/
 #define MSR_IA32_RTIT_ADDR0_A                    0x00000580
@@ -4238,6 +4516,10 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
   AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
   @endcode
+  @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.
+        MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.
+        MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.
+        MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
   @{
 **/
 #define MSR_IA32_RTIT_ADDR0_B                    0x00000581
@@ -4302,6 +4584,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
   AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
   @endcode
+  @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
 **/
 #define MSR_IA32_DS_AREA                         0x00000600
 
@@ -4321,6 +4604,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
   AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
   @endcode
+  @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
 **/
 #define MSR_IA32_TSC_DEADLINE                    0x000006E0
 
@@ -4341,6 +4625,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
   AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
 **/
 #define MSR_IA32_PM_ENABLE                       0x00000770
 
@@ -4386,6 +4671,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
   @endcode
+  @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
 **/
 #define MSR_IA32_HWP_CAPABILITIES                0x00000771
 
@@ -4447,6 +4733,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
   AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
   @endcode
+  @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
 **/
 #define MSR_IA32_HWP_REQUEST_PKG                 0x00000772
 
@@ -4508,6 +4795,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
   AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
   @endcode
+  @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
 **/
 #define MSR_IA32_HWP_INTERRUPT                   0x00000773
 
@@ -4560,6 +4848,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
   AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
   @endcode
+  @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
 **/
 #define MSR_IA32_HWP_REQUEST                     0x00000774
 
@@ -4627,6 +4916,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
   AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
 **/
 #define MSR_IA32_HWP_STATUS                      0x00000777
 
@@ -4677,6 +4967,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
   @endcode
+  @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
 **/
 #define MSR_IA32_X2APIC_APICID                   0x00000802
 
@@ -4695,6 +4986,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
   @endcode
+  @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
 **/
 #define MSR_IA32_X2APIC_VERSION                  0x00000803
 
@@ -4714,6 +5006,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
   AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
 **/
 #define MSR_IA32_X2APIC_TPR                      0x00000808
 
@@ -4732,6 +5025,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
   @endcode
+  @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
 **/
 #define MSR_IA32_X2APIC_PPR                      0x0000080A
 
@@ -4751,6 +5045,7 @@ typedef union {
   Msr = 0;
   AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
 **/
 #define MSR_IA32_X2APIC_EOI                      0x0000080B
 
@@ -4769,6 +5064,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
   @endcode
+  @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
 **/
 #define MSR_IA32_X2APIC_LDR                      0x0000080D
 
@@ -4788,6 +5084,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
   AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
 **/
 #define MSR_IA32_X2APIC_SIVR                     0x0000080F
 
@@ -4806,6 +5103,14 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
   @endcode
+  @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.
+        MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.
+        MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.
+        MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.
+        MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.
+        MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.
+        MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.
+        MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
   @{
 **/
 #define MSR_IA32_X2APIC_ISR0                     0x00000810
@@ -4833,6 +5138,14 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
   @endcode
+  @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.
+        MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.
+        MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.
+        MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.
+        MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.
+        MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.
+        MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.
+        MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
   @{
 **/
 #define MSR_IA32_X2APIC_TMR0                     0x00000818
@@ -4860,6 +5173,14 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
   @endcode
+  @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.
+        MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.
+        MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.
+        MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.
+        MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.
+        MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.
+        MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.
+        MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
   @{
 **/
 #define MSR_IA32_X2APIC_IRR0                     0x00000820
@@ -4888,6 +5209,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
   AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
 **/
 #define MSR_IA32_X2APIC_ESR                      0x00000828
 
@@ -4907,6 +5229,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
   AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
 **/
 #define MSR_IA32_X2APIC_LVT_CMCI                 0x0000082F
 
@@ -4926,6 +5249,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
   AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
 **/
 #define MSR_IA32_X2APIC_ICR                      0x00000830
 
@@ -4945,6 +5269,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
   AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
 **/
 #define MSR_IA32_X2APIC_LVT_TIMER                0x00000832
 
@@ -4964,6 +5289,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
   AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
 **/
 #define MSR_IA32_X2APIC_LVT_THERMAL              0x00000833
 
@@ -4983,6 +5309,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
   AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
 **/
 #define MSR_IA32_X2APIC_LVT_PMI                  0x00000834
 
@@ -5002,6 +5329,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
   AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
 **/
 #define MSR_IA32_X2APIC_LVT_LINT0                0x00000835
 
@@ -5021,6 +5349,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
   AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
 **/
 #define MSR_IA32_X2APIC_LVT_LINT1                0x00000836
 
@@ -5040,6 +5369,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
   AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
 **/
 #define MSR_IA32_X2APIC_LVT_ERROR                0x00000837
 
@@ -5059,6 +5389,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
   AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
 **/
 #define MSR_IA32_X2APIC_INIT_COUNT               0x00000838
 
@@ -5077,6 +5408,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
   @endcode
+  @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
 **/
 #define MSR_IA32_X2APIC_CUR_COUNT                0x00000839
 
@@ -5096,6 +5428,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
   AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
 **/
 #define MSR_IA32_X2APIC_DIV_CONF                 0x0000083E
 
@@ -5115,6 +5448,7 @@ typedef union {
   Msr = 0;
   AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
   @endcode
+  @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
 **/
 #define MSR_IA32_X2APIC_SELF_IPI                 0x0000083F
 
@@ -5135,6 +5469,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
   AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
   @endcode
+  @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
 **/
 #define MSR_IA32_DEBUG_INTERFACE                 0x00000C80
 
@@ -5192,6 +5527,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
   AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
   @endcode
+  @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
 **/
 #define MSR_IA32_L3_QOS_CFG                      0x00000C81
 
@@ -5239,6 +5575,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
   AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
 **/
 #define MSR_IA32_QM_EVTSEL                       0x00000C8D
 
@@ -5286,6 +5623,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
   @endcode
+  @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
 **/
 #define MSR_IA32_QM_CTR                          0x00000C8E
 
@@ -5340,6 +5678,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
   AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
 **/
 #define MSR_IA32_PQR_ASSOC                       0x00000C8F
 
@@ -5388,6 +5727,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
   AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
   @endcode
+  @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
 **/
 #define MSR_IA32_BNDCFGS                         0x00000D90
 
@@ -5441,6 +5781,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
   AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
   @endcode
+  @note MSR_IA32_XSS is defined as IA32_XSS in SDM.
 **/
 #define MSR_IA32_XSS                             0x00000DA0
 
@@ -5487,6 +5828,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
   AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
 **/
 #define MSR_IA32_PKG_HDC_CTL                     0x00000DB0
 
@@ -5534,6 +5876,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
   AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
   @endcode
+  @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
 **/
 #define MSR_IA32_PM_CTL1                         0x00000DB1
 
@@ -5580,6 +5923,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
   @endcode
+  @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
 **/
 #define MSR_IA32_THREAD_STALL                    0x00000DB2
 
@@ -5601,6 +5945,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
   AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
   @endcode
+  @note MSR_IA32_EFER is defined as IA32_EFER in SDM.
 **/
 #define MSR_IA32_EFER                            0xC0000080
 
@@ -5661,6 +6006,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_STAR);
   AsmWriteMsr64 (MSR_IA32_STAR, Msr);
   @endcode
+  @note MSR_IA32_STAR is defined as IA32_STAR in SDM.
 **/
 #define MSR_IA32_STAR                            0xC0000081
 
@@ -5679,6 +6025,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
   AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
   @endcode
+  @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
 **/
 #define MSR_IA32_LSTAR                           0xC0000082
 
@@ -5697,6 +6044,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_FMASK);
   AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
   @endcode
+  @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
 **/
 #define MSR_IA32_FMASK                           0xC0000084
 
@@ -5715,6 +6063,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
   AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
   @endcode
+  @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
 **/
 #define MSR_IA32_FS_BASE                         0xC0000100
 
@@ -5733,6 +6082,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
   AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
   @endcode
+  @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
 **/
 #define MSR_IA32_GS_BASE                         0xC0000101
 
@@ -5751,6 +6101,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
   AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
   @endcode
+  @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
 **/
 #define MSR_IA32_KERNEL_GS_BASE                  0xC0000102
 
@@ -5771,6 +6122,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
   AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
   @endcode
+  @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
 **/
 #define MSR_IA32_TSC_AUX                         0xC0000103
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 02/20] UefiCpuPkg/AtomMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
  2016-09-06 11:38 ` [Patch 01/20] UefiCpuPkg/ArchitecturalMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 03/20] UefiCpuPkg/BroadwellMsr.h: " Jeff Fan
                   ` (17 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 37 +++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
index 01e0d9a..25e0927 100644
--- a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
   @endcode
+  @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
 **/
 #define MSR_ATOM_PLATFORM_ID                     0x00000017
 
@@ -88,6 +89,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_ATOM_EBL_CR_POWERON                  0x0000002A
 
@@ -193,6 +195,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
   AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
   @endcode
+  @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
   @{
 **/
 #define MSR_ATOM_LASTBRANCH_0_FROM_IP            0x00000040
@@ -223,6 +233,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
   AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
   @endcode
+  @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
   @{
 **/
 #define MSR_ATOM_LASTBRANCH_0_TO_IP              0x00000060
@@ -252,6 +270,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
   @endcode
+  @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 **/
 #define MSR_ATOM_FSB_FREQ                        0x000000CD
 
@@ -310,6 +329,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_ATOM_BBL_CR_CTL3                     0x0000011E
 
@@ -368,6 +388,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
   AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
 **/
 #define MSR_ATOM_PERF_STATUS                     0x00000198
 
@@ -415,6 +436,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
   AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 **/
 #define MSR_ATOM_THERM2_CTL                      0x0000019D
 
@@ -466,6 +488,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_ATOM_IA32_MISC_ENABLE                0x000001A0
 
@@ -586,6 +609,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_ATOM_LASTBRANCH_TOS                  0x000001C9
 
@@ -605,6 +629,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
   @endcode
+  @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_ATOM_LER_FROM_LIP                    0x000001DD
 
@@ -625,6 +650,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
   @endcode
+  @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_ATOM_LER_TO_LIP                      0x000001DE
 
@@ -644,6 +670,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS, Msr);
   @endcode
+  @note MSR_ATOM_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_ATOM_IA32_PERF_GLOBAL_STAUS          0x0000038E
 
@@ -665,6 +692,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
   AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
 **/
 #define MSR_ATOM_PEBS_ENABLE                     0x000003F1
 
@@ -708,6 +736,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_MC3_CTL);
   AsmWriteMsr64 (MSR_ATOM_MC3_CTL, Msr);
   @endcode
+  @note MSR_ATOM_MC3_CTL is defined as MSR_MC3_CTL in SDM.
 **/
 #define MSR_ATOM_MC3_CTL                         0x0000040C
 
@@ -726,6 +755,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_MC3_STATUS);
   AsmWriteMsr64 (MSR_ATOM_MC3_STATUS, Msr);
   @endcode
+  @note MSR_ATOM_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
 **/
 #define MSR_ATOM_MC3_STATUS                      0x0000040D
 
@@ -748,6 +778,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_MC3_ADDR);
   AsmWriteMsr64 (MSR_ATOM_MC3_ADDR, Msr);
   @endcode
+  @note MSR_ATOM_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
 **/
 #define MSR_ATOM_MC3_ADDR                        0x0000040E
 
@@ -766,6 +797,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_MC4_CTL);
   AsmWriteMsr64 (MSR_ATOM_MC4_CTL, Msr);
   @endcode
+  @note MSR_ATOM_MC4_CTL is defined as MSR_MC4_CTL in SDM.
 **/
 #define MSR_ATOM_MC4_CTL                         0x00000410
 
@@ -784,6 +816,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_MC4_STATUS);
   AsmWriteMsr64 (MSR_ATOM_MC4_STATUS, Msr);
   @endcode
+  @note MSR_ATOM_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
 **/
 #define MSR_ATOM_MC4_STATUS                      0x00000411
 
@@ -806,6 +839,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_MC4_ADDR);
   AsmWriteMsr64 (MSR_ATOM_MC4_ADDR, Msr);
   @endcode
+  @note MSR_ATOM_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
 **/
 #define MSR_ATOM_MC4_ADDR                        0x00000412
 
@@ -828,6 +862,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
   AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
   @endcode
+  @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
 **/
 #define MSR_ATOM_PKG_C2_RESIDENCY                0x000003F8
 
@@ -850,6 +885,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
   AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
   @endcode
+  @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
 **/
 #define MSR_ATOM_PKG_C4_RESIDENCY                0x000003F9
 
@@ -872,6 +908,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
   AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
   @endcode
+  @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
 **/
 #define MSR_ATOM_PKG_C6_RESIDENCY                0x000003FA
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 03/20] UefiCpuPkg/BroadwellMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
  2016-09-06 11:38 ` [Patch 01/20] UefiCpuPkg/ArchitecturalMsr.h: " Jeff Fan
  2016-09-06 11:38 ` [Patch 02/20] UefiCpuPkg/AtomMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 04/20] UefiCpuPkg/Core2Msr.h: " Jeff Fan
                   ` (16 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
index 69c404e..0673685 100644
--- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -43,6 +43,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
   @endcode
+  @note MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS     0x0000038E
 
@@ -128,6 +129,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL     0x000000E2
 
@@ -213,6 +215,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_BROADWELL_TURBO_RATIO_LIMIT          0x000001AD
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 04/20] UefiCpuPkg/Core2Msr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (2 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 03/20] UefiCpuPkg/BroadwellMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 05/20] UefiCpuPkg/CoreMsr.h: " Jeff Fan
                   ` (15 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 52 ++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
index 5fbde51..44da688 100644
--- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
   @endcode
+  @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
 **/
 #define MSR_CORE2_PLATFORM_ID                    0x00000017
 
@@ -89,6 +90,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_CORE2_EBL_CR_POWERON                 0x0000002A
 
@@ -202,6 +204,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
   AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.
 **/
 #define MSR_CORE2_FEATURE_CONTROL                0x0000003A
 
@@ -253,6 +256,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
   AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
   @endcode
+  @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
   @{
 **/
 #define MSR_CORE2_LASTBRANCH_0_FROM_IP           0x00000040
@@ -279,6 +286,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
   AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
   @endcode
+  @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
   @{
 **/
 #define MSR_CORE2_LASTBRANCH_0_TO_IP             0x00000060
@@ -306,6 +317,7 @@ typedef union {
   Msr.Uint64 = 0;
   AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.
 **/
 #define MSR_CORE2_SMRR_PHYSBASE                  0x000000A0
 
@@ -353,6 +365,7 @@ typedef union {
   Msr.Uint64 = 0;
   AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.
 **/
 #define MSR_CORE2_SMRR_PHYSMASK                  0x000000A1
 
@@ -402,6 +415,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
   @endcode
+  @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 **/
 #define MSR_CORE2_FSB_FREQ                       0x000000CD
 
@@ -460,6 +474,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_CORE2_BBL_CR_CTL3                    0x0000011E
 
@@ -518,6 +533,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
   AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
 **/
 #define MSR_CORE2_PERF_STATUS                    0x00000198
 
@@ -577,6 +593,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
   AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 **/
 #define MSR_CORE2_THERM2_CTL                     0x0000019D
 
@@ -628,6 +645,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_CORE2_IA32_MISC_ENABLE               0x000001A0
 
@@ -795,6 +813,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_CORE2_LASTBRANCH_TOS                 0x000001C9
 
@@ -814,6 +833,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
   @endcode
+  @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_CORE2_LER_FROM_LIP                   0x000001DD
 
@@ -834,6 +854,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);
   @endcode
+  @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_CORE2_LER_TO_LIP                     0x000001DE
 
@@ -852,6 +873,9 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);
   AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);
   @endcode
+  @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.
+        MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.
+        MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.
   @{
 **/
 #define MSR_CORE2_PERF_FIXED_CTR0                0x00000309
@@ -877,6 +901,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);
   AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.
 **/
 #define MSR_CORE2_PERF_CAPABILITIES              0x00000345
 
@@ -928,6 +953,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);
   AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);
   @endcode
+  @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.
 **/
 #define MSR_CORE2_PERF_FIXED_CTR_CTRL            0x0000038D
 
@@ -947,6 +973,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS, Msr);
   @endcode
+  @note MSR_CORE2_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_CORE2_IA32_PERF_GLOBAL_STAUS         0x0000038E
 
@@ -965,6 +992,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS, Msr);
   @endcode
+  @note MSR_CORE2_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_CORE2_PERF_GLOBAL_STAUS              0x0000038E
 
@@ -983,6 +1011,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);
   AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);
   @endcode
+  @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.
 **/
 #define MSR_CORE2_PERF_GLOBAL_CTRL               0x0000038F
 
@@ -1001,6 +1030,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);
   AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);
   @endcode
+  @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
 **/
 #define MSR_CORE2_PERF_GLOBAL_OVF_CTRL           0x00000390
 
@@ -1022,6 +1052,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);
   AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
 **/
 #define MSR_CORE2_PEBS_ENABLE                    0x000003F1
 
@@ -1065,6 +1096,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC4_CTL);
   AsmWriteMsr64 (MSR_CORE2_MC4_CTL, Msr);
   @endcode
+  @note MSR_CORE2_MC4_CTL is defined as MSR_MC4_CTL in SDM.
 **/
 #define MSR_CORE2_MC4_CTL                        0x0000040C
 
@@ -1083,6 +1115,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC4_STATUS);
   AsmWriteMsr64 (MSR_CORE2_MC4_STATUS, Msr);
   @endcode
+  @note MSR_CORE2_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
 **/
 #define MSR_CORE2_MC4_STATUS                     0x0000040D
 
@@ -1105,6 +1138,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC4_ADDR);
   AsmWriteMsr64 (MSR_CORE2_MC4_ADDR, Msr);
   @endcode
+  @note MSR_CORE2_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
 **/
 #define MSR_CORE2_MC4_ADDR                       0x0000040E
 
@@ -1123,6 +1157,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC3_CTL);
   AsmWriteMsr64 (MSR_CORE2_MC3_CTL, Msr);
   @endcode
+  @note MSR_CORE2_MC3_CTL is defined as MSR_MC3_CTL in SDM.
 **/
 #define MSR_CORE2_MC3_CTL                        0x00000410
 
@@ -1141,6 +1176,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC3_STATUS);
   AsmWriteMsr64 (MSR_CORE2_MC3_STATUS, Msr);
   @endcode
+  @note MSR_CORE2_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
 **/
 #define MSR_CORE2_MC3_STATUS                     0x00000411
 
@@ -1163,6 +1199,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC3_ADDR);
   AsmWriteMsr64 (MSR_CORE2_MC3_ADDR, Msr);
   @endcode
+  @note MSR_CORE2_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
 **/
 #define MSR_CORE2_MC3_ADDR                       0x00000412
 
@@ -1181,6 +1218,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC3_MISC);
   AsmWriteMsr64 (MSR_CORE2_MC3_MISC, Msr);
   @endcode
+  @note MSR_CORE2_MC3_MISC is defined as MSR_MC3_MISC in SDM.
 **/
 #define MSR_CORE2_MC3_MISC                       0x00000413
 
@@ -1199,6 +1237,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC5_CTL);
   AsmWriteMsr64 (MSR_CORE2_MC5_CTL, Msr);
   @endcode
+  @note MSR_CORE2_MC5_CTL is defined as MSR_MC5_CTL in SDM.
 **/
 #define MSR_CORE2_MC5_CTL                        0x00000414
 
@@ -1217,6 +1256,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC5_STATUS);
   AsmWriteMsr64 (MSR_CORE2_MC5_STATUS, Msr);
   @endcode
+  @note MSR_CORE2_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
 **/
 #define MSR_CORE2_MC5_STATUS                     0x00000415
 
@@ -1235,6 +1275,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC5_ADDR);
   AsmWriteMsr64 (MSR_CORE2_MC5_ADDR, Msr);
   @endcode
+  @note MSR_CORE2_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
 **/
 #define MSR_CORE2_MC5_ADDR                       0x00000416
 
@@ -1253,6 +1294,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC5_MISC);
   AsmWriteMsr64 (MSR_CORE2_MC5_MISC, Msr);
   @endcode
+  @note MSR_CORE2_MC5_MISC is defined as MSR_MC5_MISC in SDM.
 **/
 #define MSR_CORE2_MC5_MISC                       0x00000417
 
@@ -1272,6 +1314,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC6_STATUS);
   AsmWriteMsr64 (MSR_CORE2_MC6_STATUS, Msr);
   @endcode
+  @note MSR_CORE2_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
 **/
 #define MSR_CORE2_MC6_STATUS                     0x00000419
 
@@ -1291,6 +1334,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);
   AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);
   @endcode
+  @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
   @{
 **/
 #define MSR_CORE2_EMON_L3_CTR_CTL0               0x000107CC
@@ -1319,6 +1370,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);
   AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);
   @endcode
+  @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.
 **/
 #define MSR_CORE2_EMON_L3_GL_CTL                 0x000107D8
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 05/20] UefiCpuPkg/CoreMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (3 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 04/20] UefiCpuPkg/Core2Msr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 06/20] UefiCpuPkg/HaswellEMsr.h: " Jeff Fan
                   ` (14 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 58 +++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
index 11956fb..ac45e6f 100644
--- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
 **/
 #define MSR_CORE_P5_MC_ADDR                      0x00000000
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
 **/
 #define MSR_CORE_P5_MC_TYPE                      0x00000001
 
@@ -79,6 +81,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_CORE_EBL_CR_POWERON                  0x0000002A
 
@@ -189,6 +192,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
   AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
   @endcode
+  @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
+        MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
+        MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
+        MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
+        MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
+        MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
+        MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
+        MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
   @{
 **/
 #define MSR_CORE_LASTBRANCH_0                    0x00000040
@@ -218,6 +229,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
   @endcode
+  @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 **/
 #define MSR_CORE_FSB_FREQ                        0x000000CD
 
@@ -270,6 +282,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_CORE_BBL_CR_CTL3                     0x0000011E
 
@@ -328,6 +341,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
   AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
   @endcode
+  @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 **/
 #define MSR_CORE_THERM2_CTL                      0x0000019D
 
@@ -379,6 +393,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_CORE_IA32_MISC_ENABLE                0x000001A0
 
@@ -479,6 +494,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_CORE_LASTBRANCH_TOS                  0x000001C9
 
@@ -498,6 +514,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
   @endcode
+  @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_CORE_LER_FROM_LIP                    0x000001DD
 
@@ -518,6 +535,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
   @endcode
+  @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_CORE_LER_TO_LIP                      0x000001DE
 
@@ -538,6 +556,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);
   AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);
   @endcode
+  @note MSR_CORE_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
 **/
 #define MSR_CORE_ROB_CR_BKUPTMPDR6               0x000001E0
 
@@ -582,6 +601,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
   AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
   @endcode
+  @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
+        MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
+        MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
+        MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
+        MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
+        MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
+        MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
+        MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
   @{
 **/
 #define MSR_CORE_MTRRPHYSBASE0                   0x00000200
@@ -609,6 +636,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
   AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);
   @endcode
+  @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
+        MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
+        MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
+        MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
+        MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
+        MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
+        MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
+        MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
   @{
 **/
 #define MSR_CORE_MTRRPHYSMASK0                   0x00000201
@@ -636,6 +671,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX64K_00000                0x00000250
 
@@ -654,6 +690,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX16K_80000                0x00000258
 
@@ -672,6 +709,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX16K_A0000                0x00000259
 
@@ -690,6 +728,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX4K_C0000                 0x00000268
 
@@ -708,6 +747,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX4K_C8000                 0x00000269
 
@@ -726,6 +766,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX4K_D0000                 0x0000026A
 
@@ -744,6 +785,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX4K_D8000                 0x0000026B
 
@@ -762,6 +804,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX4K_E0000                 0x0000026C
 
@@ -780,6 +823,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX4K_E8000                 0x0000026D
 
@@ -798,6 +842,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX4K_F0000                 0x0000026E
 
@@ -816,6 +861,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);
   @endcode
+  @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
 **/
 #define MSR_CORE_MTRRFIX4K_F8000                 0x0000026F
 
@@ -834,6 +880,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
   AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);
   @endcode
+  @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
 **/
 #define MSR_CORE_MC4_CTL                         0x0000040C
 
@@ -852,6 +899,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
   AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);
   @endcode
+  @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
 **/
 #define MSR_CORE_MC4_STATUS                      0x0000040D
 
@@ -874,6 +922,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
   AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);
   @endcode
+  @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
 **/
 #define MSR_CORE_MC4_ADDR                        0x0000040E
 
@@ -892,6 +941,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC3_CTL);
   AsmWriteMsr64 (MSR_CORE_MC3_CTL, Msr);
   @endcode
+  @note MSR_CORE_MC3_CTL is defined as MSR_MC3_CTL in SDM.
 **/
 #define MSR_CORE_MC3_CTL                         0x00000410
 
@@ -910,6 +960,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC3_STATUS);
   AsmWriteMsr64 (MSR_CORE_MC3_STATUS, Msr);
   @endcode
+  @note MSR_CORE_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
 **/
 #define MSR_CORE_MC3_STATUS                      0x00000411
 
@@ -932,6 +983,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
   AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);
   @endcode
+  @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
 **/
 #define MSR_CORE_MC3_ADDR                        0x00000412
 
@@ -950,6 +1002,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
   AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);
   @endcode
+  @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.
 **/
 #define MSR_CORE_MC3_MISC                        0x00000413
 
@@ -968,6 +1021,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
   AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);
   @endcode
+  @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
 **/
 #define MSR_CORE_MC5_CTL                         0x00000414
 
@@ -986,6 +1040,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
   AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);
   @endcode
+  @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
 **/
 #define MSR_CORE_MC5_STATUS                      0x00000415
 
@@ -1004,6 +1059,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
   AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);
   @endcode
+  @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
 **/
 #define MSR_CORE_MC5_ADDR                        0x00000416
 
@@ -1022,6 +1078,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
   AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);
   @endcode
+  @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
 **/
 #define MSR_CORE_MC5_MISC                        0x00000417
 
@@ -1042,6 +1099,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
   AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);
   @endcode
+  @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.
 **/
 #define MSR_CORE_IA32_EFER                       0xC0000080
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 06/20] UefiCpuPkg/HaswellEMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (4 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 05/20] UefiCpuPkg/CoreMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 07/20] UefiCpuPkg/HaswellMsr.h: " Jeff Fan
                   ` (13 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 360 ++++++++++++++++++++++++++
 1 file changed, 360 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
index ae9f406..f201e9c 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
@@ -44,6 +44,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL     0x000000E2
 
@@ -129,6 +130,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
   @endcode
+  @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
 **/
 #define MSR_HASWELL_E_IA32_MCG_CAP               0x00000179
 
@@ -208,6 +210,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
   AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
 **/
 #define MSR_HASWELL_E_SMM_MCA_CAP                0x0000017D
 
@@ -258,6 +261,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
   AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
 **/
 #define MSR_HASWELL_E_ERROR_CONTROL              0x0000017F
 
@@ -305,6 +309,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT          0x000001AD
 
@@ -380,6 +385,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
   @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
 **/
 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1         0x000001AE
 
@@ -455,6 +461,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
   @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.
 **/
 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2         0x000001AF
 
@@ -524,6 +531,23 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_MC5_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_MC5_CTL  is defined as MSR_MC5_CTL  in SDM.
+        MSR_HASWELL_E_MC6_CTL  is defined as MSR_MC6_CTL  in SDM.
+        MSR_HASWELL_E_MC7_CTL  is defined as MSR_MC7_CTL  in SDM.
+        MSR_HASWELL_E_MC8_CTL  is defined as MSR_MC8_CTL  in SDM.
+        MSR_HASWELL_E_MC9_CTL  is defined as MSR_MC9_CTL  in SDM.
+        MSR_HASWELL_E_MC10_CTL is defined as MSR_MC10_CTL in SDM.
+        MSR_HASWELL_E_MC11_CTL is defined as MSR_MC11_CTL in SDM.
+        MSR_HASWELL_E_MC12_CTL is defined as MSR_MC12_CTL in SDM.
+        MSR_HASWELL_E_MC13_CTL is defined as MSR_MC13_CTL in SDM.
+        MSR_HASWELL_E_MC14_CTL is defined as MSR_MC14_CTL in SDM.
+        MSR_HASWELL_E_MC15_CTL is defined as MSR_MC15_CTL in SDM.
+        MSR_HASWELL_E_MC16_CTL is defined as MSR_MC16_CTL in SDM.
+        MSR_HASWELL_E_MC17_CTL is defined as MSR_MC17_CTL in SDM.
+        MSR_HASWELL_E_MC18_CTL is defined as MSR_MC18_CTL in SDM.
+        MSR_HASWELL_E_MC19_CTL is defined as MSR_MC19_CTL in SDM.
+        MSR_HASWELL_E_MC20_CTL is defined as MSR_MC20_CTL in SDM.
+        MSR_HASWELL_E_MC21_CTL is defined as MSR_MC21_CTL in SDM.
   @{
 **/
 #define MSR_HASWELL_E_MC5_CTL                    0x00000414
@@ -561,6 +585,23 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_MC5_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_MC5_STATUS  is defined as MSR_MC5_STATUS  in SDM.
+        MSR_HASWELL_E_MC6_STATUS  is defined as MSR_MC6_STATUS  in SDM.
+        MSR_HASWELL_E_MC7_STATUS  is defined as MSR_MC7_STATUS  in SDM.
+        MSR_HASWELL_E_MC8_STATUS  is defined as MSR_MC8_STATUS  in SDM.
+        MSR_HASWELL_E_MC9_STATUS  is defined as MSR_MC9_STATUS  in SDM.
+        MSR_HASWELL_E_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
+        MSR_HASWELL_E_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
+        MSR_HASWELL_E_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
+        MSR_HASWELL_E_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
+        MSR_HASWELL_E_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
+        MSR_HASWELL_E_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
+        MSR_HASWELL_E_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
+        MSR_HASWELL_E_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
+        MSR_HASWELL_E_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
+        MSR_HASWELL_E_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
+        MSR_HASWELL_E_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.
+        MSR_HASWELL_E_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.
   @{
 **/
 #define MSR_HASWELL_E_MC5_STATUS                 0x00000415
@@ -597,6 +638,23 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_ADDR);
   AsmWriteMsr64 (MSR_HASWELL_E_MC5_ADDR, Msr);
   @endcode
+  @note MSR_HASWELL_E_MC5_ADDR  is defined as MSR_MC5_ADDR  in SDM.
+        MSR_HASWELL_E_MC6_ADDR  is defined as MSR_MC6_ADDR  in SDM.
+        MSR_HASWELL_E_MC7_ADDR  is defined as MSR_MC7_ADDR  in SDM.
+        MSR_HASWELL_E_MC8_ADDR  is defined as MSR_MC8_ADDR  in SDM.
+        MSR_HASWELL_E_MC9_ADDR  is defined as MSR_MC9_ADDR  in SDM.
+        MSR_HASWELL_E_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
+        MSR_HASWELL_E_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
+        MSR_HASWELL_E_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
+        MSR_HASWELL_E_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
+        MSR_HASWELL_E_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
+        MSR_HASWELL_E_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
+        MSR_HASWELL_E_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
+        MSR_HASWELL_E_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
+        MSR_HASWELL_E_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
+        MSR_HASWELL_E_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
+        MSR_HASWELL_E_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.
+        MSR_HASWELL_E_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.
   @{
 **/
 #define MSR_HASWELL_E_MC5_ADDR                   0x00000416
@@ -634,6 +692,23 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_MISC);
   AsmWriteMsr64 (MSR_HASWELL_E_MC5_MISC, Msr);
   @endcode
+  @note MSR_HASWELL_E_MC5_MISC  is defined as MSR_MC5_MISC  in SDM.
+        MSR_HASWELL_E_MC6_MISC  is defined as MSR_MC6_MISC  in SDM.
+        MSR_HASWELL_E_MC7_MISC  is defined as MSR_MC7_MISC  in SDM.
+        MSR_HASWELL_E_MC8_MISC  is defined as MSR_MC8_MISC  in SDM.
+        MSR_HASWELL_E_MC9_MISC  is defined as MSR_MC9_MISC  in SDM.
+        MSR_HASWELL_E_MC10_MISC is defined as MSR_MC10_MISC in SDM.
+        MSR_HASWELL_E_MC11_MISC is defined as MSR_MC11_MISC in SDM.
+        MSR_HASWELL_E_MC12_MISC is defined as MSR_MC12_MISC in SDM.
+        MSR_HASWELL_E_MC13_MISC is defined as MSR_MC13_MISC in SDM.
+        MSR_HASWELL_E_MC14_MISC is defined as MSR_MC14_MISC in SDM.
+        MSR_HASWELL_E_MC15_MISC is defined as MSR_MC15_MISC in SDM.
+        MSR_HASWELL_E_MC16_MISC is defined as MSR_MC16_MISC in SDM.
+        MSR_HASWELL_E_MC17_MISC is defined as MSR_MC17_MISC in SDM.
+        MSR_HASWELL_E_MC18_MISC is defined as MSR_MC18_MISC in SDM.
+        MSR_HASWELL_E_MC19_MISC is defined as MSR_MC19_MISC in SDM.
+        MSR_HASWELL_E_MC20_MISC is defined as MSR_MC20_MISC in SDM.
+        MSR_HASWELL_E_MC21_MISC is defined as MSR_MC21_MISC in SDM.
   @{
 **/
 #define MSR_HASWELL_E_MC5_MISC                   0x00000417
@@ -671,6 +746,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);
   @endcode
+  @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
 **/
 #define MSR_HASWELL_E_RAPL_POWER_UNIT            0x00000606
 
@@ -729,6 +805,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
   AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
 **/
 #define MSR_HASWELL_E_DRAM_POWER_LIMIT           0x00000618
 
@@ -746,6 +823,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
   @endcode
+  @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_DRAM_ENERGY_STATUS         0x00000619
 
@@ -764,6 +842,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);
   @endcode
+  @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_DRAM_PERF_STATUS           0x0000061B
 
@@ -782,6 +861,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
   AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);
   @endcode
+  @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
 **/
 #define MSR_HASWELL_E_DRAM_POWER_INFO            0x0000061C
 
@@ -803,6 +883,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
   AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
 **/
 #define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS    0x00000690
 
@@ -982,6 +1063,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
   AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
 **/
 #define MSR_HASWELL_E_IA32_QM_EVTSEL             0x00000C8D
 
@@ -1028,6 +1110,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
   AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
 **/
 #define MSR_HASWELL_E_IA32_PQR_ASSOC             0x00000C8F
 
@@ -1071,6 +1154,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
 **/
 #define MSR_HASWELL_E_PMON_GLOBAL_CTL            0x00000700
 
@@ -1089,6 +1173,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_PMON_GLOBAL_STATUS         0x00000701
 
@@ -1107,6 +1192,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
   AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);
   @endcode
+  @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
 **/
 #define MSR_HASWELL_E_PMON_GLOBAL_CONFIG         0x00000702
 
@@ -1125,6 +1211,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
 **/
 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL      0x00000703
 
@@ -1143,6 +1230,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);
   @endcode
+  @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
 **/
 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR      0x00000704
 
@@ -1161,6 +1249,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_U_PMON_EVNTSEL0            0x00000705
 
@@ -1179,6 +1268,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_U_PMON_EVNTSEL1            0x00000706
 
@@ -1197,6 +1287,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_U_PMON_BOX_STATUS          0x00000708
 
@@ -1215,6 +1306,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_U_PMON_CTR0                0x00000709
 
@@ -1233,6 +1325,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_U_PMON_CTR1                0x0000070A
 
@@ -1251,6 +1344,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_BOX_CTL           0x00000710
 
@@ -1269,6 +1363,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL0          0x00000711
 
@@ -1287,6 +1382,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL1          0x00000712
 
@@ -1305,6 +1401,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL2          0x00000713
 
@@ -1323,6 +1420,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL3          0x00000714
 
@@ -1341,6 +1439,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_BOX_FILTER        0x00000715
 
@@ -1359,6 +1458,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_BOX_STATUS        0x00000716
 
@@ -1377,6 +1477,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_CTR0              0x00000717
 
@@ -1395,6 +1496,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_CTR1              0x00000718
 
@@ -1413,6 +1515,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_CTR2              0x00000719
 
@@ -1431,6 +1534,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_PCU_PMON_CTR3              0x0000071A
 
@@ -1449,6 +1553,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_S0_PMON_BOX_CTL            0x00000720
 
@@ -1467,6 +1572,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_S0_PMON_EVNTSEL0           0x00000721
 
@@ -1485,6 +1591,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_S0_PMON_EVNTSEL1           0x00000722
 
@@ -1503,6 +1610,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_S0_PMON_EVNTSEL2           0x00000723
 
@@ -1521,6 +1629,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_S0_PMON_EVNTSEL3           0x00000724
 
@@ -1539,6 +1648,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_HASWELL_E_S0_PMON_BOX_FILTER         0x00000725
 
@@ -1557,6 +1667,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_S0_PMON_CTR0               0x00000726
 
@@ -1575,6 +1686,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_S0_PMON_CTR1               0x00000727
 
@@ -1593,6 +1705,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_S0_PMON_CTR2               0x00000728
 
@@ -1611,6 +1724,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_S0_PMON_CTR3               0x00000729
 
@@ -1629,6 +1743,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_S1_PMON_BOX_CTL            0x0000072A
 
@@ -1647,6 +1762,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_S1_PMON_EVNTSEL0           0x0000072B
 
@@ -1665,6 +1781,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_S1_PMON_EVNTSEL1           0x0000072C
 
@@ -1683,6 +1800,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_S1_PMON_EVNTSEL2           0x0000072D
 
@@ -1701,6 +1819,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_S1_PMON_EVNTSEL3           0x0000072E
 
@@ -1719,6 +1838,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_HASWELL_E_S1_PMON_BOX_FILTER         0x0000072F
 
@@ -1737,6 +1857,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_S1_PMON_CTR0               0x00000730
 
@@ -1755,6 +1876,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_S1_PMON_CTR1               0x00000731
 
@@ -1773,6 +1895,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_S1_PMON_CTR2               0x00000732
 
@@ -1791,6 +1914,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_S1_PMON_CTR3               0x00000733
 
@@ -1809,6 +1933,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_S2_PMON_BOX_CTL            0x00000734
 
@@ -1827,6 +1952,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_S2_PMON_EVNTSEL0           0x00000735
 
@@ -1845,6 +1971,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_S2_PMON_EVNTSEL1           0x00000736
 
@@ -1863,6 +1990,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_S2_PMON_EVNTSEL2           0x00000737
 
@@ -1881,6 +2009,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_S2_PMON_EVNTSEL3           0x00000738
 
@@ -1899,6 +2028,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_HASWELL_E_S2_PMON_BOX_FILTER         0x00000739
 
@@ -1917,6 +2047,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_S2_PMON_CTR0               0x0000073A
 
@@ -1935,6 +2066,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_S2_PMON_CTR1               0x0000073B
 
@@ -1953,6 +2085,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_S2_PMON_CTR2               0x0000073C
 
@@ -1971,6 +2104,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_S2_PMON_CTR3               0x0000073D
 
@@ -1989,6 +2123,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_S3_PMON_BOX_CTL            0x0000073E
 
@@ -2007,6 +2142,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_S3_PMON_EVNTSEL0           0x0000073F
 
@@ -2025,6 +2161,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_S3_PMON_EVNTSEL1           0x00000740
 
@@ -2043,6 +2180,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_S3_PMON_EVNTSEL2           0x00000741
 
@@ -2061,6 +2199,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_S3_PMON_EVNTSEL3           0x00000742
 
@@ -2079,6 +2218,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_HASWELL_E_S3_PMON_BOX_FILTER         0x00000743
 
@@ -2097,6 +2237,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_S3_PMON_CTR0               0x00000744
 
@@ -2115,6 +2256,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_S3_PMON_CTR1               0x00000745
 
@@ -2133,6 +2275,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_S3_PMON_CTR2               0x00000746
 
@@ -2151,6 +2294,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_S3_PMON_CTR3               0x00000747
 
@@ -2169,6 +2313,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_BOX_CTL            0x00000E00
 
@@ -2187,6 +2332,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_EVNTSEL0           0x00000E01
 
@@ -2205,6 +2351,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_EVNTSEL1           0x00000E02
 
@@ -2223,6 +2370,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_EVNTSEL2           0x00000E03
 
@@ -2241,6 +2389,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_EVNTSEL3           0x00000E04
 
@@ -2259,6 +2408,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER0        0x00000E05
 
@@ -2277,6 +2427,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER1        0x00000E06
 
@@ -2295,6 +2446,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_BOX_STATUS         0x00000E07
 
@@ -2313,6 +2465,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_CTR0               0x00000E08
 
@@ -2331,6 +2484,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_CTR1               0x00000E09
 
@@ -2349,6 +2503,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_CTR2               0x00000E0A
 
@@ -2367,6 +2522,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C0_PMON_CTR3               0x00000E0B
 
@@ -2385,6 +2541,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_BOX_CTL            0x00000E10
 
@@ -2403,6 +2560,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_EVNTSEL0           0x00000E11
 
@@ -2421,6 +2579,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_EVNTSEL1           0x00000E12
 
@@ -2439,6 +2598,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_EVNTSEL2           0x00000E13
 
@@ -2457,6 +2617,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_EVNTSEL3           0x00000E14
 
@@ -2475,6 +2636,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER0        0x00000E15
 
@@ -2493,6 +2655,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER1        0x00000E16
 
@@ -2511,6 +2674,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_BOX_STATUS         0x00000E17
 
@@ -2529,6 +2693,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_CTR0               0x00000E18
 
@@ -2547,6 +2712,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_CTR1               0x00000E19
 
@@ -2565,6 +2731,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_CTR2               0x00000E1A
 
@@ -2583,6 +2750,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C1_PMON_CTR3               0x00000E1B
 
@@ -2601,6 +2769,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_BOX_CTL            0x00000E20
 
@@ -2619,6 +2788,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_EVNTSEL0           0x00000E21
 
@@ -2637,6 +2807,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_EVNTSEL1           0x00000E22
 
@@ -2655,6 +2826,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_EVNTSEL2           0x00000E23
 
@@ -2673,6 +2845,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_EVNTSEL3           0x00000E24
 
@@ -2691,6 +2864,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER0        0x00000E25
 
@@ -2709,6 +2883,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER1        0x00000E26
 
@@ -2727,6 +2902,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_BOX_STATUS         0x00000E27
 
@@ -2745,6 +2921,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_CTR0               0x00000E28
 
@@ -2763,6 +2940,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_CTR1               0x00000E29
 
@@ -2781,6 +2959,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_CTR2               0x00000E2A
 
@@ -2799,6 +2978,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C2_PMON_CTR3               0x00000E2B
 
@@ -2817,6 +2997,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_BOX_CTL            0x00000E30
 
@@ -2835,6 +3016,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_EVNTSEL0           0x00000E31
 
@@ -2853,6 +3035,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_EVNTSEL1           0x00000E32
 
@@ -2871,6 +3054,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_EVNTSEL2           0x00000E33
 
@@ -2889,6 +3073,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_EVNTSEL3           0x00000E34
 
@@ -2907,6 +3092,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER0        0x00000E35
 
@@ -2925,6 +3111,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER1        0x00000E36
 
@@ -2943,6 +3130,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_BOX_STATUS         0x00000E37
 
@@ -2961,6 +3149,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_CTR0               0x00000E38
 
@@ -2979,6 +3168,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_CTR1               0x00000E39
 
@@ -2997,6 +3187,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_CTR2               0x00000E3A
 
@@ -3015,6 +3206,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C3_PMON_CTR3               0x00000E3B
 
@@ -3033,6 +3225,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_BOX_CTL            0x00000E40
 
@@ -3051,6 +3244,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_EVNTSEL0           0x00000E41
 
@@ -3069,6 +3263,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_EVNTSEL1           0x00000E42
 
@@ -3087,6 +3282,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_EVNTSEL2           0x00000E43
 
@@ -3105,6 +3301,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_EVNTSEL3           0x00000E44
 
@@ -3123,6 +3320,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER0        0x00000E45
 
@@ -3141,6 +3339,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER1        0x00000E46
 
@@ -3159,6 +3358,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_BOX_STATUS         0x00000E47
 
@@ -3177,6 +3377,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_CTR0               0x00000E48
 
@@ -3195,6 +3396,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_CTR1               0x00000E49
 
@@ -3213,6 +3415,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_CTR2               0x00000E4A
 
@@ -3231,6 +3434,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C4_PMON_CTR3               0x00000E4B
 
@@ -3249,6 +3453,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_BOX_CTL            0x00000E50
 
@@ -3267,6 +3472,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_EVNTSEL0           0x00000E51
 
@@ -3285,6 +3491,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_EVNTSEL1           0x00000E52
 
@@ -3303,6 +3510,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_EVNTSEL2           0x00000E53
 
@@ -3321,6 +3529,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_EVNTSEL3           0x00000E54
 
@@ -3339,6 +3548,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER0        0x00000E55
 
@@ -3357,6 +3567,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER1        0x00000E56
 
@@ -3375,6 +3586,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_BOX_STATUS         0x00000E57
 
@@ -3393,6 +3605,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_CTR0               0x00000E58
 
@@ -3411,6 +3624,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_CTR1               0x00000E59
 
@@ -3429,6 +3643,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_CTR2               0x00000E5A
 
@@ -3447,6 +3662,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C5_PMON_CTR3               0x00000E5B
 
@@ -3465,6 +3681,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_BOX_CTL            0x00000E60
 
@@ -3483,6 +3700,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_EVNTSEL0           0x00000E61
 
@@ -3501,6 +3719,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_EVNTSEL1           0x00000E62
 
@@ -3519,6 +3738,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_EVNTSEL2           0x00000E63
 
@@ -3537,6 +3757,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_EVNTSEL3           0x00000E64
 
@@ -3555,6 +3776,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER0        0x00000E65
 
@@ -3573,6 +3795,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER1        0x00000E66
 
@@ -3591,6 +3814,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_BOX_STATUS         0x00000E67
 
@@ -3609,6 +3833,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_CTR0               0x00000E68
 
@@ -3627,6 +3852,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_CTR1               0x00000E69
 
@@ -3645,6 +3871,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_CTR2               0x00000E6A
 
@@ -3663,6 +3890,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C6_PMON_CTR3               0x00000E6B
 
@@ -3681,6 +3909,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_BOX_CTL            0x00000E70
 
@@ -3699,6 +3928,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_EVNTSEL0           0x00000E71
 
@@ -3717,6 +3947,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_EVNTSEL1           0x00000E72
 
@@ -3735,6 +3966,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_EVNTSEL2           0x00000E73
 
@@ -3753,6 +3985,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_EVNTSEL3           0x00000E74
 
@@ -3771,6 +4004,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER0        0x00000E75
 
@@ -3789,6 +4023,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER1        0x00000E76
 
@@ -3807,6 +4042,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_BOX_STATUS         0x00000E77
 
@@ -3825,6 +4061,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_CTR0               0x00000E78
 
@@ -3843,6 +4080,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_CTR1               0x00000E79
 
@@ -3861,6 +4099,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_CTR2               0x00000E7A
 
@@ -3879,6 +4118,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C7_PMON_CTR3               0x00000E7B
 
@@ -3897,6 +4137,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_BOX_CTL            0x00000E80
 
@@ -3915,6 +4156,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_EVNTSEL0           0x00000E81
 
@@ -3933,6 +4175,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_EVNTSEL1           0x00000E82
 
@@ -3951,6 +4194,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_EVNTSEL2           0x00000E83
 
@@ -3969,6 +4213,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_EVNTSEL3           0x00000E84
 
@@ -3987,6 +4232,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER0        0x00000E85
 
@@ -4005,6 +4251,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER1        0x00000E86
 
@@ -4023,6 +4270,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_BOX_STATUS         0x00000E87
 
@@ -4041,6 +4289,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_CTR0               0x00000E88
 
@@ -4059,6 +4308,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_CTR1               0x00000E89
 
@@ -4077,6 +4327,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_CTR2               0x00000E8A
 
@@ -4095,6 +4346,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C8_PMON_CTR3               0x00000E8B
 
@@ -4113,6 +4365,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_BOX_CTL            0x00000E90
 
@@ -4131,6 +4384,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_EVNTSEL0           0x00000E91
 
@@ -4149,6 +4403,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_EVNTSEL1           0x00000E92
 
@@ -4167,6 +4422,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_EVNTSEL2           0x00000E93
 
@@ -4185,6 +4441,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_EVNTSEL3           0x00000E94
 
@@ -4203,6 +4460,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER0        0x00000E95
 
@@ -4221,6 +4479,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER1        0x00000E96
 
@@ -4239,6 +4498,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_BOX_STATUS         0x00000E97
 
@@ -4257,6 +4517,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_CTR0               0x00000E98
 
@@ -4275,6 +4536,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_CTR1               0x00000E99
 
@@ -4293,6 +4555,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_CTR2               0x00000E9A
 
@@ -4311,6 +4574,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C9_PMON_CTR3               0x00000E9B
 
@@ -4329,6 +4593,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_BOX_CTL           0x00000EA0
 
@@ -4347,6 +4612,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_EVNTSEL0          0x00000EA1
 
@@ -4365,6 +4631,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_EVNTSEL1          0x00000EA2
 
@@ -4383,6 +4650,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_EVNTSEL2          0x00000EA3
 
@@ -4401,6 +4669,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_EVNTSEL3          0x00000EA4
 
@@ -4419,6 +4688,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER0       0x00000EA5
 
@@ -4437,6 +4707,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER1       0x00000EA6
 
@@ -4455,6 +4726,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_BOX_STATUS        0x00000EA7
 
@@ -4473,6 +4745,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_CTR0              0x00000EA8
 
@@ -4491,6 +4764,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_CTR1              0x00000EA9
 
@@ -4509,6 +4783,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_CTR2              0x00000EAA
 
@@ -4527,6 +4802,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C10_PMON_CTR3              0x00000EAB
 
@@ -4545,6 +4821,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_BOX_CTL           0x00000EB0
 
@@ -4563,6 +4840,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_EVNTSEL0          0x00000EB1
 
@@ -4581,6 +4859,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_EVNTSEL1          0x00000EB2
 
@@ -4599,6 +4878,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_EVNTSEL2          0x00000EB3
 
@@ -4617,6 +4897,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_EVNTSEL3          0x00000EB4
 
@@ -4635,6 +4916,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER0       0x00000EB5
 
@@ -4653,6 +4935,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER1       0x00000EB6
 
@@ -4671,6 +4954,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_BOX_STATUS        0x00000EB7
 
@@ -4689,6 +4973,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_CTR0              0x00000EB8
 
@@ -4707,6 +4992,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_CTR1              0x00000EB9
 
@@ -4725,6 +5011,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_CTR2              0x00000EBA
 
@@ -4743,6 +5030,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C11_PMON_CTR3              0x00000EBB
 
@@ -4761,6 +5049,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_BOX_CTL           0x00000EC0
 
@@ -4779,6 +5068,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_EVNTSEL0          0x00000EC1
 
@@ -4797,6 +5087,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_EVNTSEL1          0x00000EC2
 
@@ -4815,6 +5106,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_EVNTSEL2          0x00000EC3
 
@@ -4833,6 +5125,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_EVNTSEL3          0x00000EC4
 
@@ -4851,6 +5144,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER0       0x00000EC5
 
@@ -4869,6 +5163,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER1       0x00000EC6
 
@@ -4887,6 +5182,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_BOX_STATUS        0x00000EC7
 
@@ -4905,6 +5201,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_CTR0              0x00000EC8
 
@@ -4923,6 +5220,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_CTR1              0x00000EC9
 
@@ -4941,6 +5239,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_CTR2              0x00000ECA
 
@@ -4959,6 +5258,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C12_PMON_CTR3              0x00000ECB
 
@@ -4977,6 +5277,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_BOX_CTL           0x00000ED0
 
@@ -4995,6 +5296,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_EVNTSEL0          0x00000ED1
 
@@ -5013,6 +5315,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_EVNTSEL1          0x00000ED2
 
@@ -5031,6 +5334,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_EVNTSEL2          0x00000ED3
 
@@ -5049,6 +5353,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_EVNTSEL3          0x00000ED4
 
@@ -5067,6 +5372,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER0       0x00000ED5
 
@@ -5085,6 +5391,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER1       0x00000ED6
 
@@ -5103,6 +5410,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_BOX_STATUS        0x00000ED7
 
@@ -5121,6 +5429,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_CTR0              0x00000ED8
 
@@ -5139,6 +5448,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_CTR1              0x00000ED9
 
@@ -5157,6 +5467,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_CTR2              0x00000EDA
 
@@ -5175,6 +5486,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C13_PMON_CTR3              0x00000EDB
 
@@ -5193,6 +5505,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_BOX_CTL           0x00000EE0
 
@@ -5211,6 +5524,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_EVNTSEL0          0x00000EE1
 
@@ -5229,6 +5543,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_EVNTSEL1          0x00000EE2
 
@@ -5247,6 +5562,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_EVNTSEL2          0x00000EE3
 
@@ -5265,6 +5581,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_EVNTSEL3          0x00000EE4
 
@@ -5283,6 +5600,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER        0x00000EE5
 
@@ -5301,6 +5619,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER1       0x00000EE6
 
@@ -5319,6 +5638,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_BOX_STATUS        0x00000EE7
 
@@ -5337,6 +5657,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_CTR0              0x00000EE8
 
@@ -5355,6 +5676,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_CTR1              0x00000EE9
 
@@ -5373,6 +5695,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_CTR2              0x00000EEA
 
@@ -5391,6 +5714,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C14_PMON_CTR3              0x00000EEB
 
@@ -5409,6 +5733,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_BOX_CTL           0x00000EF0
 
@@ -5427,6 +5752,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_EVNTSEL0          0x00000EF1
 
@@ -5445,6 +5771,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_EVNTSEL1          0x00000EF2
 
@@ -5463,6 +5790,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_EVNTSEL2          0x00000EF3
 
@@ -5481,6 +5809,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_EVNTSEL3          0x00000EF4
 
@@ -5499,6 +5828,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER0       0x00000EF5
 
@@ -5517,6 +5847,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER1       0x00000EF6
 
@@ -5535,6 +5866,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_BOX_STATUS        0x00000EF7
 
@@ -5553,6 +5885,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_CTR0              0x00000EF8
 
@@ -5571,6 +5904,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_CTR1              0x00000EF9
 
@@ -5589,6 +5923,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_CTR2              0x00000EFA
 
@@ -5607,6 +5942,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C15_PMON_CTR3              0x00000EFB
 
@@ -5625,6 +5961,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_BOX_CTL           0x00000F00
 
@@ -5643,6 +5980,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_EVNTSEL0          0x00000F01
 
@@ -5661,6 +5999,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_EVNTSEL1          0x00000F02
 
@@ -5679,6 +6018,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_EVNTSEL2          0x00000F03
 
@@ -5697,6 +6037,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_EVNTSEL3          0x00000F04
 
@@ -5715,6 +6056,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER0       0x00000F05
 
@@ -5733,6 +6075,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER1       0x00000F06
 
@@ -5751,6 +6094,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_BOX_STATUS        0x00000F07
 
@@ -5769,6 +6113,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_CTR0              0x00000F08
 
@@ -5787,6 +6132,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_CTR1              0x00000F09
 
@@ -5805,6 +6151,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_CTR2              0x00000F0A
 
@@ -5823,6 +6170,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.
 **/
 #define MSR_HASWELL_E_C16_PMON_CTR3              0x00000E0B
 
@@ -5841,6 +6189,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.
 **/
 #define MSR_HASWELL_E_C17_PMON_BOX_CTL           0x00000F10
 
@@ -5859,6 +6208,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_HASWELL_E_C17_PMON_EVNTSEL0          0x00000F11
 
@@ -5877,6 +6227,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_HASWELL_E_C17_PMON_EVNTSEL1          0x00000F12
 
@@ -5895,6 +6246,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_HASWELL_E_C17_PMON_EVNTSEL2          0x00000F13
 
@@ -5913,6 +6265,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_HASWELL_E_C17_PMON_EVNTSEL3          0x00000F14
 
@@ -5931,6 +6284,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.
 **/
 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER0       0x00000F15
 
@@ -5949,6 +6303,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER1       0x00000F16
 
@@ -5966,6 +6321,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_HASWELL_E_C17_PMON_BOX_STATUS        0x00000F17
 
@@ -5984,6 +6340,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);
   @endcode
+  @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.
+        MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.
+        MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.
+        MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.
   @{
 **/
 #define MSR_HASWELL_E_C17_PMON_CTR0              0x00000F18
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 07/20] UefiCpuPkg/HaswellMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (5 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 06/20] UefiCpuPkg/HaswellEMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 08/20] UefiCpuPkg/IvyBridgeMsr.h: " Jeff Fan
                   ` (12 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 58 ++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
index 78915ec..f7cb6ce 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -42,6 +42,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_HASWELL_PLATFORM_INFO                0x000000CE
 
@@ -126,6 +127,9 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
+        MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
+        MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
   @{
 **/
 #define MSR_HASWELL_IA32_PERFEVTSEL0             0x00000186
@@ -226,6 +230,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);
   AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
 **/
 #define MSR_HASWELL_IA32_PERFEVTSEL2             0x00000188
 
@@ -330,6 +335,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);
   AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
 **/
 #define MSR_HASWELL_LBR_SELECT                   0x000001C8
 
@@ -416,6 +422,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);
   AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
 **/
 #define MSR_HASWELL_PKGC_IRTL1                   0x0000060B
 
@@ -487,6 +494,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);
   AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
 **/
 #define MSR_HASWELL_PKGC_IRTL2                   0x0000060C
 
@@ -550,6 +558,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);
   @endcode
+  @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
 **/
 #define MSR_HASWELL_PKG_PERF_STATUS              0x00000613
 
@@ -567,6 +576,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);
   @endcode
+  @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
 **/
 #define MSR_HASWELL_DRAM_ENERGY_STATUS           0x00000619
 
@@ -585,6 +595,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);
   @endcode
+  @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
 **/
 #define MSR_HASWELL_DRAM_PERF_STATUS             0x0000061B
 
@@ -604,6 +615,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);
   @endcode
+  @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
 **/
 #define MSR_HASWELL_CONFIG_TDP_NOMINAL           0x00000648
 
@@ -649,6 +661,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);
   @endcode
+  @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
 **/
 #define MSR_HASWELL_CONFIG_TDP_LEVEL1            0x00000649
 
@@ -705,6 +718,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);
   @endcode
+  @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
 **/
 #define MSR_HASWELL_CONFIG_TDP_LEVEL2            0x0000064A
 
@@ -762,6 +776,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);
   AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
 **/
 #define MSR_HASWELL_CONFIG_TDP_CONTROL           0x0000064B
 
@@ -812,6 +827,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);
   AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
 **/
 #define MSR_HASWELL_TURBO_ACTIVATION_RATIO       0x0000064C
 
@@ -861,6 +877,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE);
   AsmWriteMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE, Msr);
   @endcode
+  @note MSR_HASWELL_IA32_DEBUG_FEATURE is defined as IA32_DEBUG_FEATURE in SDM.
 **/
 #define MSR_HASWELL_IA32_DEBUG_FEATURE           0x00000C80
 
@@ -883,6 +900,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_HASWELL_PKG_CST_CONFIG_CONTROL       0x000000E2
 
@@ -962,6 +980,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);
   AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
 **/
 #define MSR_HASWELL_SMM_MCA_CAP                  0x0000017D
 
@@ -1012,6 +1031,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_HASWELL_TURBO_RATIO_LIMIT            0x000001AD
 
@@ -1072,6 +1092,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);
   AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
 **/
 #define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL         0x00000391
 
@@ -1142,6 +1163,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);
   AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
 **/
 #define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS       0x00000392
 
@@ -1196,6 +1218,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);
   AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
 **/
 #define MSR_HASWELL_UNC_PERF_FIXED_CTRL          0x00000394
 
@@ -1247,6 +1270,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);
   AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
 **/
 #define MSR_HASWELL_UNC_PERF_FIXED_CTR           0x00000395
 
@@ -1290,6 +1314,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_CONFIG               0x00000396
 
@@ -1333,6 +1358,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);
   AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
 **/
 #define MSR_HASWELL_UNC_ARB_PERFCTR0             0x000003B0
 
@@ -1351,6 +1377,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);
   AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
 **/
 #define MSR_HASWELL_UNC_ARB_PERFCTR1             0x000003B1
 
@@ -1369,6 +1396,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
 **/
 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL0          0x000003B2
 
@@ -1387,6 +1415,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
 **/
 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL1          0x000003B3
 
@@ -1408,6 +1437,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);
   AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
 **/
 #define MSR_HASWELL_SMM_FEATURE_CONTROL          0x000004E0
 
@@ -1481,6 +1511,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);
   @endcode
+  @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
 **/
 #define MSR_HASWELL_SMM_DELAYED                  0x000004E2
 
@@ -1514,6 +1545,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);
   @endcode
+  @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
 **/
 #define MSR_HASWELL_SMM_BLOCKED                  0x000004E3
 
@@ -1533,6 +1565,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);
   @endcode
+  @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
 **/
 #define MSR_HASWELL_RAPL_POWER_UNIT              0x00000606
 
@@ -1591,6 +1624,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);
   AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
 **/
 #define MSR_HASWELL_PP1_POWER_LIMIT              0x00000640
 
@@ -1609,6 +1643,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);
   @endcode
+  @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
 **/
 #define MSR_HASWELL_PP1_ENERGY_STATUS            0x00000641
 
@@ -1628,6 +1663,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);
   AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);
   @endcode
+  @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
 **/
 #define MSR_HASWELL_PP1_POLICY                   0x00000642
 
@@ -1649,6 +1685,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);
   AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
 **/
 #define MSR_HASWELL_CORE_PERF_LIMIT_REASONS      0x00000690
 
@@ -1831,6 +1868,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);
   AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
 **/
 #define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS  0x000006B0
 
@@ -2002,6 +2040,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);
   AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
 **/
 #define MSR_HASWELL_RING_PERF_LIMIT_REASONS      0x000006B1
 
@@ -2152,6 +2191,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0        0x00000700
 
@@ -2170,6 +2210,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1        0x00000701
 
@@ -2188,6 +2229,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_0_PERFCTR0           0x00000706
 
@@ -2206,6 +2248,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_0_PERFCTR1           0x00000707
 
@@ -2224,6 +2267,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0        0x00000710
 
@@ -2242,6 +2286,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1        0x00000711
 
@@ -2260,6 +2305,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_1_PERFCTR0           0x00000716
 
@@ -2278,6 +2324,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_1_PERFCTR1           0x00000717
 
@@ -2296,6 +2343,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0        0x00000720
 
@@ -2314,6 +2362,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1        0x00000721
 
@@ -2332,6 +2381,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_2_PERFCTR0           0x00000726
 
@@ -2350,6 +2400,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_2_PERFCTR1           0x00000727
 
@@ -2368,6 +2419,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0        0x00000730
 
@@ -2386,6 +2438,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1        0x00000731
 
@@ -2404,6 +2457,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_3_PERFCTR0           0x00000736
 
@@ -2422,6 +2476,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);
   AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);
   @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
 **/
 #define MSR_HASWELL_UNC_CBO_3_PERFCTR1           0x00000737
 
@@ -2443,6 +2498,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);
   AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.
 **/
 #define MSR_HASWELL_PKG_C8_RESIDENCY             0x00000630
 
@@ -2492,6 +2548,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);
   AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.
 **/
 #define MSR_HASWELL_PKG_C9_RESIDENCY             0x00000631
 
@@ -2541,6 +2598,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);
   AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);
   @endcode
+  @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
 **/
 #define MSR_HASWELL_PKG_C10_RESIDENCY            0x00000632
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 08/20] UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (6 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 07/20] UefiCpuPkg/HaswellMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 09/20] UefiCpuPkg/NehalemMsr.h: " Jeff Fan
                   ` (11 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 218 +++++++++++++++++++++++++
 1 file changed, 218 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
index 0b08c0a..d278d52 100644
--- a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -42,6 +42,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_IVY_BRIDGE_PLATFORM_INFO             0x000000CE
 
@@ -127,6 +128,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL    0x000000E2
 
@@ -213,6 +215,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);
   @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
 **/
 #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL        0x00000648
 
@@ -258,6 +261,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);
   @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1         0x00000649
 
@@ -315,6 +319,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);
   @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2         0x0000064A
 
@@ -373,6 +378,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
 **/
 #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL        0x0000064B
 
@@ -423,6 +429,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
 **/
 #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO    0x0000064C
 
@@ -474,6 +481,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
 **/
 #define MSR_IVY_BRIDGE_PPIN_CTL                  0x0000004E
 
@@ -535,6 +543,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);
   @endcode
+  @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.
 **/
 #define MSR_IVY_BRIDGE_PPIN                      0x0000004F
 
@@ -555,6 +564,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_PLATFORM_INFO_1           0x000000CE
 
@@ -636,6 +646,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
 **/
 #define MSR_IVY_BRIDGE_ERROR_CONTROL             0x0000017F
 
@@ -683,6 +694,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
 **/
 #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET        0x000001A2
 
@@ -737,6 +749,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);
   @endcode
+  @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1        0x000001AE
 
@@ -822,6 +835,33 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_CTL, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_MC5_CTL  is defined as MSR_MC5_CTL  in SDM.
+        MSR_IVY_BRIDGE_MC6_CTL  is defined as MSR_MC6_CTL  in SDM.
+        MSR_IVY_BRIDGE_MC7_CTL  is defined as MSR_MC7_CTL  in SDM.
+        MSR_IVY_BRIDGE_MC8_CTL  is defined as MSR_MC8_CTL  in SDM.
+        MSR_IVY_BRIDGE_MC9_CTL  is defined as MSR_MC9_CTL  in SDM.
+        MSR_IVY_BRIDGE_MC10_CTL is defined as MSR_MC10_CTL in SDM.
+        MSR_IVY_BRIDGE_MC11_CTL is defined as MSR_MC11_CTL in SDM.
+        MSR_IVY_BRIDGE_MC12_CTL is defined as MSR_MC12_CTL in SDM.
+        MSR_IVY_BRIDGE_MC13_CTL is defined as MSR_MC13_CTL in SDM.
+        MSR_IVY_BRIDGE_MC14_CTL is defined as MSR_MC14_CTL in SDM.
+        MSR_IVY_BRIDGE_MC15_CTL is defined as MSR_MC15_CTL in SDM.
+        MSR_IVY_BRIDGE_MC16_CTL is defined as MSR_MC16_CTL in SDM.
+        MSR_IVY_BRIDGE_MC17_CTL is defined as MSR_MC17_CTL in SDM.
+        MSR_IVY_BRIDGE_MC18_CTL is defined as MSR_MC18_CTL in SDM.
+        MSR_IVY_BRIDGE_MC19_CTL is defined as MSR_MC19_CTL in SDM.
+        MSR_IVY_BRIDGE_MC20_CTL is defined as MSR_MC20_CTL in SDM.
+        MSR_IVY_BRIDGE_MC21_CTL is defined as MSR_MC21_CTL in SDM.
+        MSR_IVY_BRIDGE_MC22_CTL is defined as MSR_MC22_CTL in SDM.
+        MSR_IVY_BRIDGE_MC23_CTL is defined as MSR_MC23_CTL in SDM.
+        MSR_IVY_BRIDGE_MC24_CTL is defined as MSR_MC24_CTL in SDM.
+        MSR_IVY_BRIDGE_MC25_CTL is defined as MSR_MC25_CTL in SDM.
+        MSR_IVY_BRIDGE_MC26_CTL is defined as MSR_MC26_CTL in SDM.
+        MSR_IVY_BRIDGE_MC27_CTL is defined as MSR_MC27_CTL in SDM.
+        MSR_IVY_BRIDGE_MC28_CTL is defined as MSR_MC28_CTL in SDM.
+        MSR_IVY_BRIDGE_MC29_CTL is defined as MSR_MC29_CTL in SDM.
+        MSR_IVY_BRIDGE_MC30_CTL is defined as MSR_MC30_CTL in SDM.
+        MSR_IVY_BRIDGE_MC31_CTL is defined as MSR_MC31_CTL in SDM.
   @{
 **/
 #define MSR_IVY_BRIDGE_MC5_CTL                   0x00000414
@@ -872,6 +912,33 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_STATUS);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_STATUS, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_MC5_STATUS  is defined as MSR_MC5_STATUS  in SDM.
+        MSR_IVY_BRIDGE_MC6_STATUS  is defined as MSR_MC6_STATUS  in SDM.
+        MSR_IVY_BRIDGE_MC7_STATUS  is defined as MSR_MC7_STATUS  in SDM.
+        MSR_IVY_BRIDGE_MC8_STATUS  is defined as MSR_MC8_STATUS  in SDM.
+        MSR_IVY_BRIDGE_MC9_STATUS  is defined as MSR_MC9_STATUS  in SDM.
+        MSR_IVY_BRIDGE_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC22_STATUS is defined as MSR_MC22_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC23_STATUS is defined as MSR_MC23_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC24_STATUS is defined as MSR_MC24_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC25_STATUS is defined as MSR_MC25_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC26_STATUS is defined as MSR_MC26_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC27_STATUS is defined as MSR_MC27_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC28_STATUS is defined as MSR_MC28_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC29_STATUS is defined as MSR_MC29_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC30_STATUS is defined as MSR_MC30_STATUS in SDM.
+        MSR_IVY_BRIDGE_MC31_STATUS is defined as MSR_MC31_STATUS in SDM.
   @{
 **/
 #define MSR_IVY_BRIDGE_MC5_STATUS                0x00000415
@@ -919,6 +986,33 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_ADDR);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_ADDR, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_MC5_ADDR  is defined as MSR_MC5_ADDR  in SDM.
+        MSR_IVY_BRIDGE_MC6_ADDR  is defined as MSR_MC6_ADDR  in SDM.
+        MSR_IVY_BRIDGE_MC7_ADDR  is defined as MSR_MC7_ADDR  in SDM.
+        MSR_IVY_BRIDGE_MC8_ADDR  is defined as MSR_MC8_ADDR  in SDM.
+        MSR_IVY_BRIDGE_MC9_ADDR  is defined as MSR_MC9_ADDR  in SDM.
+        MSR_IVY_BRIDGE_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC22_ADDR is defined as MSR_MC22_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC23_ADDR is defined as MSR_MC23_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC24_ADDR is defined as MSR_MC24_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC25_ADDR is defined as MSR_MC25_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC26_ADDR is defined as MSR_MC26_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC27_ADDR is defined as MSR_MC27_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC28_ADDR is defined as MSR_MC28_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC29_ADDR is defined as MSR_MC29_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC30_ADDR is defined as MSR_MC30_ADDR in SDM.
+        MSR_IVY_BRIDGE_MC31_ADDR is defined as MSR_MC31_ADDR in SDM.
   @{
 **/
 #define MSR_IVY_BRIDGE_MC5_ADDR                  0x00000416
@@ -966,6 +1060,33 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_MISC);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_MISC, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_MC5_MISC  is defined as MSR_MC5_MISC  in SDM.
+        MSR_IVY_BRIDGE_MC6_MISC  is defined as MSR_MC6_MISC  in SDM.
+        MSR_IVY_BRIDGE_MC7_MISC  is defined as MSR_MC7_MISC  in SDM.
+        MSR_IVY_BRIDGE_MC8_MISC  is defined as MSR_MC8_MISC  in SDM.
+        MSR_IVY_BRIDGE_MC9_MISC  is defined as MSR_MC9_MISC  in SDM.
+        MSR_IVY_BRIDGE_MC10_MISC is defined as MSR_MC10_MISC in SDM.
+        MSR_IVY_BRIDGE_MC11_MISC is defined as MSR_MC11_MISC in SDM.
+        MSR_IVY_BRIDGE_MC12_MISC is defined as MSR_MC12_MISC in SDM.
+        MSR_IVY_BRIDGE_MC13_MISC is defined as MSR_MC13_MISC in SDM.
+        MSR_IVY_BRIDGE_MC14_MISC is defined as MSR_MC14_MISC in SDM.
+        MSR_IVY_BRIDGE_MC15_MISC is defined as MSR_MC15_MISC in SDM.
+        MSR_IVY_BRIDGE_MC16_MISC is defined as MSR_MC16_MISC in SDM.
+        MSR_IVY_BRIDGE_MC17_MISC is defined as MSR_MC17_MISC in SDM.
+        MSR_IVY_BRIDGE_MC18_MISC is defined as MSR_MC18_MISC in SDM.
+        MSR_IVY_BRIDGE_MC19_MISC is defined as MSR_MC19_MISC in SDM.
+        MSR_IVY_BRIDGE_MC20_MISC is defined as MSR_MC20_MISC in SDM.
+        MSR_IVY_BRIDGE_MC21_MISC is defined as MSR_MC21_MISC in SDM.
+        MSR_IVY_BRIDGE_MC22_MISC is defined as MSR_MC22_MISC in SDM.
+        MSR_IVY_BRIDGE_MC23_MISC is defined as MSR_MC23_MISC in SDM.
+        MSR_IVY_BRIDGE_MC24_MISC is defined as MSR_MC24_MISC in SDM.
+        MSR_IVY_BRIDGE_MC25_MISC is defined as MSR_MC25_MISC in SDM.
+        MSR_IVY_BRIDGE_MC26_MISC is defined as MSR_MC26_MISC in SDM.
+        MSR_IVY_BRIDGE_MC27_MISC is defined as MSR_MC27_MISC in SDM.
+        MSR_IVY_BRIDGE_MC28_MISC is defined as MSR_MC28_MISC in SDM.
+        MSR_IVY_BRIDGE_MC29_MISC is defined as MSR_MC29_MISC in SDM.
+        MSR_IVY_BRIDGE_MC30_MISC is defined as MSR_MC30_MISC in SDM.
+        MSR_IVY_BRIDGE_MC31_MISC is defined as MSR_MC31_MISC in SDM.
   @{
 **/
 #define MSR_IVY_BRIDGE_MC5_MISC                  0x00000417
@@ -1013,6 +1134,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
   @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
 **/
 #define MSR_IVY_BRIDGE_IA32_MC6_MISC             0x0000041B
 
@@ -1063,6 +1185,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);
   @endcode
+  @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
 **/
 #define MSR_IVY_BRIDGE_PKG_PERF_STATUS           0x00000613
 
@@ -1082,6 +1205,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
 **/
 #define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT          0x00000618
 
@@ -1099,6 +1223,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);
   @endcode
+  @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
 **/
 #define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS        0x00000619
 
@@ -1117,6 +1242,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);
   @endcode
+  @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
 **/
 #define MSR_IVY_BRIDGE_DRAM_PERF_STATUS          0x0000061B
 
@@ -1135,6 +1261,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
 **/
 #define MSR_IVY_BRIDGE_DRAM_POWER_INFO           0x0000061C
 
@@ -1155,6 +1282,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
 **/
 #define MSR_IVY_BRIDGE_PEBS_ENABLE               0x000003F1
 
@@ -1222,6 +1350,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
 **/
 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL           0x00000C00
 
@@ -1240,6 +1369,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
 **/
 #define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS        0x00000C01
 
@@ -1258,6 +1388,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
 **/
 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG        0x00000C06
 
@@ -1276,6 +1407,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS         0x00000C15
 
@@ -1294,6 +1426,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS       0x00000C35
 
@@ -1312,6 +1445,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1       0x00000D1A
 
@@ -1330,6 +1464,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1       0x00000D3A
 
@@ -1348,6 +1483,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1       0x00000D5A
 
@@ -1366,6 +1502,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1       0x00000D7A
 
@@ -1384,6 +1521,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1       0x00000D9A
 
@@ -1402,6 +1540,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1       0x00000DBA
 
@@ -1420,6 +1559,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1       0x00000DDA
 
@@ -1438,6 +1578,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1       0x00000DFA
 
@@ -1456,6 +1597,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL           0x00000E04
 
@@ -1474,6 +1616,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0          0x00000E10
 
@@ -1492,6 +1635,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1          0x00000E11
 
@@ -1510,6 +1654,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2          0x00000E12
 
@@ -1528,6 +1673,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3          0x00000E13
 
@@ -1546,6 +1692,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER        0x00000E14
 
@@ -1564,6 +1711,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_CTR0              0x00000E16
 
@@ -1582,6 +1730,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_CTR1              0x00000E17
 
@@ -1600,6 +1749,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_CTR2              0x00000E18
 
@@ -1618,6 +1768,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_CTR3              0x00000E19
 
@@ -1636,6 +1787,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1       0x00000E1A
 
@@ -1654,6 +1806,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL           0x00000E24
 
@@ -1672,6 +1825,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0          0x00000E30
 
@@ -1690,6 +1844,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1          0x00000E31
 
@@ -1708,6 +1863,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2          0x00000E32
 
@@ -1726,6 +1882,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3          0x00000E33
 
@@ -1744,6 +1901,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER        0x00000E34
 
@@ -1762,6 +1920,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_CTR0              0x00000E36
 
@@ -1780,6 +1939,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_CTR1              0x00000E37
 
@@ -1798,6 +1958,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_CTR2              0x00000E38
 
@@ -1816,6 +1977,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_CTR3              0x00000E39
 
@@ -1834,6 +1996,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1       0x00000E3A
 
@@ -1852,6 +2015,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL          0x00000E44
 
@@ -1870,6 +2034,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0         0x00000E50
 
@@ -1888,6 +2053,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1         0x00000E51
 
@@ -1906,6 +2072,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2         0x00000E52
 
@@ -1924,6 +2091,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3         0x00000E53
 
@@ -1942,6 +2110,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER       0x00000E54
 
@@ -1960,6 +2129,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_CTR0             0x00000E56
 
@@ -1978,6 +2148,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_CTR1             0x00000E57
 
@@ -1996,6 +2167,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_CTR2             0x00000E58
 
@@ -2014,6 +2186,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_CTR3             0x00000E59
 
@@ -2032,6 +2205,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1      0x00000E5A
 
@@ -2050,6 +2224,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL          0x00000E64
 
@@ -2068,6 +2243,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0         0x00000E70
 
@@ -2086,6 +2262,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1         0x00000E71
 
@@ -2104,6 +2281,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2         0x00000E72
 
@@ -2122,6 +2300,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3         0x00000E73
 
@@ -2140,6 +2319,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER       0x00000E74
 
@@ -2158,6 +2338,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_CTR0             0x00000E76
 
@@ -2176,6 +2357,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_CTR1             0x00000E77
 
@@ -2194,6 +2376,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_CTR2             0x00000E78
 
@@ -2212,6 +2395,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_CTR3             0x00000E79
 
@@ -2230,6 +2414,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1      0x00000E7A
 
@@ -2248,6 +2433,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL          0x00000E84
 
@@ -2266,6 +2452,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0         0x00000E90
 
@@ -2284,6 +2471,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1         0x00000E91
 
@@ -2302,6 +2490,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2         0x00000E92
 
@@ -2320,6 +2509,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3         0x00000E93
 
@@ -2338,6 +2528,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER       0x00000E94
 
@@ -2356,6 +2547,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_CTR0             0x00000E96
 
@@ -2374,6 +2566,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_CTR1             0x00000E97
 
@@ -2392,6 +2585,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_CTR2             0x00000E98
 
@@ -2410,6 +2604,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_CTR3             0x00000E99
 
@@ -2428,6 +2623,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1      0x00000E9A
 
@@ -2446,6 +2642,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL          0x00000EA4
 
@@ -2464,6 +2661,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0         0x00000EB0
 
@@ -2482,6 +2680,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1         0x00000EB1
 
@@ -2500,6 +2699,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2         0x00000EB2
 
@@ -2518,6 +2718,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3         0x00000EB3
 
@@ -2536,6 +2737,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER       0x00000EB4
 
@@ -2554,6 +2756,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_CTR0             0x00000EB6
 
@@ -2572,6 +2775,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_CTR1             0x00000EB7
 
@@ -2590,6 +2794,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_CTR2             0x00000EB8
 
@@ -2608,6 +2813,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_CTR3             0x00000EB9
 
@@ -2626,6 +2832,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1      0x00000EBA
 
@@ -2644,6 +2851,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL          0x00000EC4
 
@@ -2662,6 +2870,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0         0x00000ED0
 
@@ -2680,6 +2889,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1         0x00000ED1
 
@@ -2698,6 +2908,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2         0x00000ED2
 
@@ -2716,6 +2927,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3         0x00000ED3
 
@@ -2734,6 +2946,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER       0x00000ED4
 
@@ -2752,6 +2965,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_CTR0             0x00000ED6
 
@@ -2770,6 +2984,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_CTR1             0x00000ED7
 
@@ -2788,6 +3003,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_CTR2             0x00000ED8
 
@@ -2806,6 +3022,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_CTR3             0x00000ED9
 
@@ -2824,6 +3041,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);
   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);
   @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
 **/
 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1      0x00000EDA
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 09/20] UefiCpuPkg/NehalemMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (7 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 08/20] UefiCpuPkg/IvyBridgeMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 10/20] UefiCpuPkg/P6Msr.h: " Jeff Fan
                   ` (10 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 465 +++++++++++++++++++++++++++
 1 file changed, 465 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
index cc24a23..6f3d4f4 100644
--- a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);
   @endcode
+  @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
 **/
 #define MSR_NEHALEM_PLATFORM_ID                  0x00000017
 
@@ -82,6 +83,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);
   @endcode
+  @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 **/
 #define MSR_NEHALEM_SMI_COUNT                    0x00000034
 
@@ -127,6 +129,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_NEHALEM_PLATFORM_INFO                0x000000CE
 
@@ -195,6 +198,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL       0x000000E2
 
@@ -281,6 +285,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
   AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
 **/
 #define MSR_NEHALEM_PMG_IO_CAPTURE_BASE          0x000000E4
 
@@ -340,6 +345,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_NEHALEM_IA32_MISC_ENABLE             0x000001A0
 
@@ -440,6 +446,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
 **/
 #define MSR_NEHALEM_TEMPERATURE_TARGET           0x000001A2
 
@@ -487,6 +494,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
   AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
 **/
 #define MSR_NEHALEM_MISC_FEATURE_CONTROL         0x000001A4
 
@@ -551,6 +559,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
   AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);
   @endcode
+  @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
 **/
 #define MSR_NEHALEM_OFFCORE_RSP_0                0x000001A6
 
@@ -571,6 +580,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
   AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
 **/
 #define MSR_NEHALEM_MISC_PWR_MGMT                0x000001AA
 
@@ -626,6 +636,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
   AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.
 **/
 #define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT    0x000001AC
 
@@ -686,6 +697,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_NEHALEM_TURBO_RATIO_LIMIT            0x000001AD
 
@@ -747,6 +759,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
   AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
 **/
 #define MSR_NEHALEM_LBR_SELECT                   0x000001C8
 
@@ -824,6 +837,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_NEHALEM_LASTBRANCH_TOS               0x000001C9
 
@@ -843,6 +857,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);
   @endcode
+  @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_NEHALEM_LER_FROM_LIP                 0x000001DD
 
@@ -863,6 +878,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);
   @endcode
+  @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_NEHALEM_LER_TO_LIP                   0x000001DE
 
@@ -883,6 +899,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);
   AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.
 **/
 #define MSR_NEHALEM_POWER_CTL                    0x000001FC
 
@@ -930,6 +947,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS, Msr);
   @endcode
+  @note MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS       0x0000038E
 
@@ -949,6 +967,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STAUS);
   @endcode
+  @note MSR_NEHALEM_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_NEHALEM_PERF_GLOBAL_STAUS            0x0000038E
 
@@ -991,6 +1010,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL         0x00000390
 
@@ -1033,6 +1053,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);
   AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
 **/
 #define MSR_NEHALEM_PEBS_ENABLE                  0x000003F1
 
@@ -1103,6 +1124,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);
   AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
 **/
 #define MSR_NEHALEM_PEBS_LD_LAT                  0x000003F6
 
@@ -1150,6 +1172,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);
   AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);
   @endcode
+  @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
 **/
 #define MSR_NEHALEM_PKG_C3_RESIDENCY             0x000003F8
 
@@ -1171,6 +1194,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);
   AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);
   @endcode
+  @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
 **/
 #define MSR_NEHALEM_PKG_C6_RESIDENCY             0x000003F9
 
@@ -1192,6 +1216,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);
   AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);
   @endcode
+  @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
 **/
 #define MSR_NEHALEM_PKG_C7_RESIDENCY             0x000003FA
 
@@ -1213,6 +1238,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);
   AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);
   @endcode
+  @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
 **/
 #define MSR_NEHALEM_CORE_C3_RESIDENCY            0x000003FC
 
@@ -1234,6 +1260,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);
   AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);
   @endcode
+  @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
 **/
 #define MSR_NEHALEM_CORE_C6_RESIDENCY            0x000003FD
 
@@ -1252,6 +1279,28 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_MC0_MISC);
   AsmWriteMsr64 (MSR_NEHALEM_MC0_MISC, Msr);
   @endcode
+  @note MSR_NEHALEM_MC0_MISC  is defined as MSR_MC0_MISC  in SDM.
+        MSR_NEHALEM_MC1_MISC  is defined as MSR_MC1_MISC  in SDM.
+        MSR_NEHALEM_MC2_MISC  is defined as MSR_MC2_MISC  in SDM.
+        MSR_NEHALEM_MC3_MISC  is defined as MSR_MC3_MISC  in SDM.
+        MSR_NEHALEM_MC4_MISC  is defined as MSR_MC4_MISC  in SDM.
+        MSR_NEHALEM_MC5_MISC  is defined as MSR_MC5_MISC  in SDM.
+        MSR_NEHALEM_MC6_MISC  is defined as MSR_MC6_MISC  in SDM.
+        MSR_NEHALEM_MC7_MISC  is defined as MSR_MC7_MISC  in SDM.
+        MSR_NEHALEM_MC8_MISC  is defined as MSR_MC8_MISC  in SDM.
+        MSR_NEHALEM_MC9_MISC  is defined as MSR_MC9_MISC  in SDM.
+        MSR_NEHALEM_MC10_MISC is defined as MSR_MC10_MISC in SDM.
+        MSR_NEHALEM_MC11_MISC is defined as MSR_MC11_MISC in SDM.
+        MSR_NEHALEM_MC12_MISC is defined as MSR_MC12_MISC in SDM.
+        MSR_NEHALEM_MC13_MISC is defined as MSR_MC13_MISC in SDM.
+        MSR_NEHALEM_MC14_MISC is defined as MSR_MC14_MISC in SDM.
+        MSR_NEHALEM_MC15_MISC is defined as MSR_MC15_MISC in SDM.
+        MSR_NEHALEM_MC16_MISC is defined as MSR_MC16_MISC in SDM.
+        MSR_NEHALEM_MC17_MISC is defined as MSR_MC17_MISC in SDM.
+        MSR_NEHALEM_MC18_MISC is defined as MSR_MC18_MISC in SDM.
+        MSR_NEHALEM_MC19_MISC is defined as MSR_MC19_MISC in SDM.
+        MSR_NEHALEM_MC20_MISC is defined as MSR_MC20_MISC in SDM.
+        MSR_NEHALEM_MC21_MISC is defined as MSR_MC21_MISC in SDM.
   @{
 **/
 #define MSR_NEHALEM_MC0_MISC                     0x00000403
@@ -1293,6 +1342,25 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_CTL);
   AsmWriteMsr64 (MSR_NEHALEM_MC3_CTL, Msr);
   @endcode
+  @note MSR_NEHALEM_MC3_CTL  is defined as MSR_MC3_CTL  in SDM.
+        MSR_NEHALEM_MC4_CTL  is defined as MSR_MC4_CTL  in SDM.
+        MSR_NEHALEM_MC5_CTL  is defined as MSR_MC5_CTL  in SDM.
+        MSR_NEHALEM_MC6_CTL  is defined as MSR_MC6_CTL  in SDM.
+        MSR_NEHALEM_MC7_CTL  is defined as MSR_MC7_CTL  in SDM.
+        MSR_NEHALEM_MC8_CTL  is defined as MSR_MC8_CTL  in SDM.
+        MSR_NEHALEM_MC9_CTL  is defined as MSR_MC9_CTL  in SDM.
+        MSR_NEHALEM_MC10_CTL is defined as MSR_MC10_CTL in SDM.
+        MSR_NEHALEM_MC11_CTL is defined as MSR_MC11_CTL in SDM.
+        MSR_NEHALEM_MC12_CTL is defined as MSR_MC12_CTL in SDM.
+        MSR_NEHALEM_MC13_CTL is defined as MSR_MC13_CTL in SDM.
+        MSR_NEHALEM_MC14_CTL is defined as MSR_MC14_CTL in SDM.
+        MSR_NEHALEM_MC15_CTL is defined as MSR_MC15_CTL in SDM.
+        MSR_NEHALEM_MC16_CTL is defined as MSR_MC16_CTL in SDM.
+        MSR_NEHALEM_MC17_CTL is defined as MSR_MC17_CTL in SDM.
+        MSR_NEHALEM_MC18_CTL is defined as MSR_MC18_CTL in SDM.
+        MSR_NEHALEM_MC19_CTL is defined as MSR_MC19_CTL in SDM.
+        MSR_NEHALEM_MC20_CTL is defined as MSR_MC20_CTL in SDM.
+        MSR_NEHALEM_MC21_CTL is defined as MSR_MC21_CTL in SDM.
   @{
 **/
 #define MSR_NEHALEM_MC3_CTL                      0x0000040C
@@ -1331,6 +1399,25 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_MC3_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_MC3_STATUS  is defined as MSR_MC3_STATUS  in SDM.
+        MSR_NEHALEM_MC4_STATUS  is defined as MSR_MC4_STATUS  in SDM.
+        MSR_NEHALEM_MC5_STATUS  is defined as MSR_MC5_STATUS  in SDM.
+        MSR_NEHALEM_MC6_STATUS  is defined as MSR_MC6_STATUS  in SDM.
+        MSR_NEHALEM_MC7_STATUS  is defined as MSR_MC7_STATUS  in SDM.
+        MSR_NEHALEM_MC8_STATUS  is defined as MSR_MC8_STATUS  in SDM.
+        MSR_NEHALEM_MC9_STATUS  is defined as MSR_MC9_STATUS  in SDM.
+        MSR_NEHALEM_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
+        MSR_NEHALEM_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
+        MSR_NEHALEM_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
+        MSR_NEHALEM_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
+        MSR_NEHALEM_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
+        MSR_NEHALEM_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
+        MSR_NEHALEM_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
+        MSR_NEHALEM_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
+        MSR_NEHALEM_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
+        MSR_NEHALEM_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
+        MSR_NEHALEM_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.
+        MSR_NEHALEM_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.
   @{
 **/
 #define MSR_NEHALEM_MC3_STATUS                   0x0000040D
@@ -1379,6 +1466,25 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_ADDR);
   AsmWriteMsr64 (MSR_NEHALEM_MC3_ADDR, Msr);
   @endcode
+  @note MSR_NEHALEM_MC3_ADDR  is defined as MSR_MC3_ADDR  in SDM.
+        MSR_NEHALEM_MC4_ADDR  is defined as MSR_MC4_ADDR  in SDM.
+        MSR_NEHALEM_MC5_ADDR  is defined as MSR_MC5_ADDR  in SDM.
+        MSR_NEHALEM_MC6_ADDR  is defined as MSR_MC6_ADDR  in SDM.
+        MSR_NEHALEM_MC7_ADDR  is defined as MSR_MC7_ADDR  in SDM.
+        MSR_NEHALEM_MC8_ADDR  is defined as MSR_MC8_ADDR  in SDM.
+        MSR_NEHALEM_MC9_ADDR  is defined as MSR_MC9_ADDR  in SDM.
+        MSR_NEHALEM_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
+        MSR_NEHALEM_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
+        MSR_NEHALEM_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
+        MSR_NEHALEM_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
+        MSR_NEHALEM_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
+        MSR_NEHALEM_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
+        MSR_NEHALEM_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
+        MSR_NEHALEM_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
+        MSR_NEHALEM_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
+        MSR_NEHALEM_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
+        MSR_NEHALEM_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.
+        MSR_NEHALEM_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.
   @{
 **/
 #define MSR_NEHALEM_MC3_ADDR                     0x0000040E
@@ -1422,6 +1528,22 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
   AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);
   @endcode
+  @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP  is defined as MSR_LASTBRANCH_0_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_1_FROM_IP  is defined as MSR_LASTBRANCH_1_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_2_FROM_IP  is defined as MSR_LASTBRANCH_2_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_3_FROM_IP  is defined as MSR_LASTBRANCH_3_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_4_FROM_IP  is defined as MSR_LASTBRANCH_4_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_5_FROM_IP  is defined as MSR_LASTBRANCH_5_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_6_FROM_IP  is defined as MSR_LASTBRANCH_6_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_7_FROM_IP  is defined as MSR_LASTBRANCH_7_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_8_FROM_IP  is defined as MSR_LASTBRANCH_8_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_9_FROM_IP  is defined as MSR_LASTBRANCH_9_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
   @{
 **/
 #define MSR_NEHALEM_LASTBRANCH_0_FROM_IP         0x00000680
@@ -1460,6 +1582,22 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
   AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);
   @endcode
+  @note MSR_NEHALEM_LASTBRANCH_0_TO_IP  is defined as MSR_LASTBRANCH_0_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_1_TO_IP  is defined as MSR_LASTBRANCH_1_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_2_TO_IP  is defined as MSR_LASTBRANCH_2_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_3_TO_IP  is defined as MSR_LASTBRANCH_3_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_4_TO_IP  is defined as MSR_LASTBRANCH_4_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_5_TO_IP  is defined as MSR_LASTBRANCH_5_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_6_TO_IP  is defined as MSR_LASTBRANCH_6_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_7_TO_IP  is defined as MSR_LASTBRANCH_7_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_8_TO_IP  is defined as MSR_LASTBRANCH_8_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_9_TO_IP  is defined as MSR_LASTBRANCH_9_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
   @{
 **/
 #define MSR_NEHALEM_LASTBRANCH_0_TO_IP           0x000006C0
@@ -1497,6 +1635,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);
   AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);
   @endcode
+  @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.
 **/
 #define MSR_NEHALEM_GQ_SNOOP_MESF                0x00000301
 
@@ -1569,6 +1708,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.
 **/
 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL      0x00000391
 
@@ -1588,6 +1728,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.
 **/
 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS    0x00000392
 
@@ -1607,6 +1748,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL  0x00000393
 
@@ -1626,6 +1768,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_UNCORE_FIXED_CTR0            0x00000394
 
@@ -1645,6 +1788,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.
 **/
 #define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL        0x00000395
 
@@ -1663,6 +1807,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);
   AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);
   @endcode
+  @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.
 **/
 #define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH     0x00000396
 
@@ -1682,6 +1827,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
   AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);
   @endcode
+  @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.
+        MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.
+        MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.
+        MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.
+        MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.
+        MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.
+        MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.
+        MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.
   @{
 **/
 #define MSR_NEHALEM_UNCORE_PMC0                  0x000003B0
@@ -1709,6 +1862,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.
   @{
 **/
 #define MSR_NEHALEM_UNCORE_PERFEVTSEL0           0x000003C0
@@ -1736,6 +1897,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_FIXED_CTR             0x00000394
 
@@ -1754,6 +1916,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL         0x00000395
 
@@ -1772,6 +1935,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.
 **/
 #define MSR_NEHALEM_U_PMON_GLOBAL_CTRL           0x00000C00
 
@@ -1790,6 +1954,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.
 **/
 #define MSR_NEHALEM_U_PMON_GLOBAL_STATUS         0x00000C01
 
@@ -1808,6 +1973,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL       0x00000C02
 
@@ -1826,6 +1992,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);
   AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);
   @endcode
+  @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.
 **/
 #define MSR_NEHALEM_U_PMON_EVNT_SEL              0x00000C10
 
@@ -1844,6 +2011,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);
   AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);
   @endcode
+  @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.
 **/
 #define MSR_NEHALEM_U_PMON_CTR                   0x00000C11
 
@@ -1862,6 +2030,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_BOX_CTRL             0x00000C20
 
@@ -1880,6 +2049,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_BOX_STATUS           0x00000C21
 
@@ -1898,6 +2068,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL         0x00000C22
 
@@ -1916,6 +2087,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_EVNT_SEL0            0x00000C30
 
@@ -1934,6 +2106,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_CTR0                 0x00000C31
 
@@ -1952,6 +2125,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_EVNT_SEL1            0x00000C32
 
@@ -1970,6 +2144,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_CTR1                 0x00000C33
 
@@ -1988,6 +2163,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_EVNT_SEL2            0x00000C34
 
@@ -2006,6 +2182,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_CTR2                 0x00000C35
 
@@ -2024,6 +2201,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_EVNT_SEL3            0x00000C36
 
@@ -2042,6 +2220,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_CTR3                 0x00000C37
 
@@ -2060,6 +2239,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_BOX_CTRL             0x00000C40
 
@@ -2078,6 +2258,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_BOX_STATUS           0x00000C41
 
@@ -2096,6 +2277,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL         0x00000C42
 
@@ -2114,6 +2296,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_EVNT_SEL0            0x00000C50
 
@@ -2132,6 +2315,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_CTR0                 0x00000C51
 
@@ -2150,6 +2334,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_EVNT_SEL1            0x00000C52
 
@@ -2168,6 +2353,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_CTR1                 0x00000C53
 
@@ -2186,6 +2372,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_EVNT_SEL2            0x00000C54
 
@@ -2204,6 +2391,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_CTR2                 0x00000C55
 
@@ -2222,6 +2410,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_EVNT_SEL3            0x00000C56
 
@@ -2240,6 +2429,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_CTR3                 0x00000C57
 
@@ -2258,6 +2448,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_BOX_CTRL             0x00000C60
 
@@ -2276,6 +2467,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_BOX_STATUS           0x00000C61
 
@@ -2294,6 +2486,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL         0x00000C62
 
@@ -2312,6 +2505,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_EVNT_SEL0            0x00000C70
 
@@ -2330,6 +2524,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_CTR0                 0x00000C71
 
@@ -2348,6 +2543,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_EVNT_SEL1            0x00000C72
 
@@ -2366,6 +2562,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_CTR1                 0x00000C73
 
@@ -2384,6 +2581,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_EVNT_SEL2            0x00000C74
 
@@ -2402,6 +2600,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_CTR2                 0x00000C75
 
@@ -2420,6 +2619,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_EVNT_SEL3            0x00000C76
 
@@ -2438,6 +2638,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_CTR3                 0x00000C77
 
@@ -2456,6 +2657,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_BOX_CTRL              0x00000C80
 
@@ -2474,6 +2676,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_BOX_STATUS            0x00000C81
 
@@ -2492,6 +2695,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL          0x00000C82
 
@@ -2510,6 +2714,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_EVNT_SEL0             0x00000C90
 
@@ -2528,6 +2733,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_CTR0                  0x00000C91
 
@@ -2546,6 +2752,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_EVNT_SEL1             0x00000C92
 
@@ -2564,6 +2771,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_CTR1                  0x00000C93
 
@@ -2582,6 +2790,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_EVNT_SEL2             0x00000C94
 
@@ -2600,6 +2809,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_CTR2                  0x00000C95
 
@@ -2618,6 +2828,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_EVNT_SEL3             0x00000C96
 
@@ -2636,6 +2847,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_W_PMON_CTR3                  0x00000C97
 
@@ -2654,6 +2866,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_BOX_CTRL             0x00000CA0
 
@@ -2672,6 +2885,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_BOX_STATUS           0x00000CA1
 
@@ -2690,6 +2904,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL         0x00000CA2
 
@@ -2708,6 +2923,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_TIMESTAMP            0x00000CA4
 
@@ -2726,6 +2942,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_DSP                  0x00000CA5
 
@@ -2744,6 +2961,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_ISS                  0x00000CA6
 
@@ -2762,6 +2980,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_MAP                  0x00000CA7
 
@@ -2780,6 +2999,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_MSC_THR              0x00000CA8
 
@@ -2798,6 +3018,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_PGT                  0x00000CA9
 
@@ -2816,6 +3037,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_PLD                  0x00000CAA
 
@@ -2834,6 +3056,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_ZDP                  0x00000CAB
 
@@ -2852,6 +3075,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_EVNT_SEL0            0x00000CB0
 
@@ -2870,6 +3094,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_CTR0                 0x00000CB1
 
@@ -2888,6 +3113,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_EVNT_SEL1            0x00000CB2
 
@@ -2906,6 +3132,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_CTR1                 0x00000CB3
 
@@ -2924,6 +3151,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_EVNT_SEL2            0x00000CB4
 
@@ -2942,6 +3170,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_CTR2                 0x00000CB5
 
@@ -2960,6 +3189,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_EVNT_SEL3            0x00000CB6
 
@@ -2978,6 +3208,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_CTR3                 0x00000CB7
 
@@ -2996,6 +3227,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_EVNT_SEL4            0x00000CB8
 
@@ -3014,6 +3246,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_CTR4                 0x00000CB9
 
@@ -3032,6 +3265,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_EVNT_SEL5            0x00000CBA
 
@@ -3050,6 +3284,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_CTR5                 0x00000CBB
 
@@ -3068,6 +3303,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_BOX_CTRL             0x00000CC0
 
@@ -3086,6 +3322,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_BOX_STATUS           0x00000CC1
 
@@ -3104,6 +3341,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL         0x00000CC2
 
@@ -3122,6 +3360,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_EVNT_SEL0            0x00000CD0
 
@@ -3140,6 +3379,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_CTR0                 0x00000CD1
 
@@ -3158,6 +3398,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_EVNT_SEL1            0x00000CD2
 
@@ -3176,6 +3417,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_CTR1                 0x00000CD3
 
@@ -3194,6 +3436,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_EVNT_SEL2            0x00000CD4
 
@@ -3212,6 +3455,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_CTR2                 0x00000CD5
 
@@ -3230,6 +3474,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_EVNT_SEL3            0x00000CD6
 
@@ -3248,6 +3493,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_CTR3                 0x00000CD7
 
@@ -3266,6 +3512,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_BOX_CTRL             0x00000CE0
 
@@ -3284,6 +3531,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_BOX_STATUS           0x00000CE1
 
@@ -3302,6 +3550,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL         0x00000CE2
 
@@ -3320,6 +3569,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_TIMESTAMP            0x00000CE4
 
@@ -3338,6 +3588,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_DSP                  0x00000CE5
 
@@ -3356,6 +3607,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_ISS                  0x00000CE6
 
@@ -3374,6 +3626,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_MAP                  0x00000CE7
 
@@ -3392,6 +3645,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_MSC_THR              0x00000CE8
 
@@ -3410,6 +3664,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_PGT                  0x00000CE9
 
@@ -3428,6 +3683,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_PLD                  0x00000CEA
 
@@ -3446,6 +3702,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_ZDP                  0x00000CEB
 
@@ -3464,6 +3721,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_EVNT_SEL0            0x00000CF0
 
@@ -3482,6 +3740,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_CTR0                 0x00000CF1
 
@@ -3500,6 +3759,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_EVNT_SEL1            0x00000CF2
 
@@ -3518,6 +3778,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_CTR1                 0x00000CF3
 
@@ -3536,6 +3797,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_EVNT_SEL2            0x00000CF4
 
@@ -3554,6 +3816,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_CTR2                 0x00000CF5
 
@@ -3572,6 +3835,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_EVNT_SEL3            0x00000CF6
 
@@ -3590,6 +3854,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_CTR3                 0x00000CF7
 
@@ -3608,6 +3873,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_EVNT_SEL4            0x00000CF8
 
@@ -3626,6 +3892,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_CTR4                 0x00000CF9
 
@@ -3644,6 +3911,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_EVNT_SEL5            0x00000CFA
 
@@ -3662,6 +3930,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_CTR5                 0x00000CFB
 
@@ -3680,6 +3949,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_BOX_CTRL             0x00000D00
 
@@ -3698,6 +3968,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_BOX_STATUS           0x00000D01
 
@@ -3716,6 +3987,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL         0x00000D02
 
@@ -3734,6 +4006,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_EVNT_SEL0            0x00000D10
 
@@ -3752,6 +4025,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_CTR0                 0x00000D11
 
@@ -3770,6 +4044,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_EVNT_SEL1            0x00000D12
 
@@ -3788,6 +4063,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_CTR1                 0x00000D13
 
@@ -3806,6 +4082,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_EVNT_SEL2            0x00000D14
 
@@ -3824,6 +4101,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_CTR2                 0x00000D15
 
@@ -3842,6 +4120,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_EVNT_SEL3            0x00000D16
 
@@ -3860,6 +4139,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_CTR3                 0x00000D17
 
@@ -3878,6 +4158,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_EVNT_SEL4            0x00000D18
 
@@ -3896,6 +4177,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_CTR4                 0x00000D19
 
@@ -3914,6 +4196,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_EVNT_SEL5            0x00000D1A
 
@@ -3932,6 +4215,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_C0_PMON_CTR5                 0x00000D1B
 
@@ -3950,6 +4234,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_BOX_CTRL             0x00000D20
 
@@ -3968,6 +4253,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_BOX_STATUS           0x00000D21
 
@@ -3986,6 +4272,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL         0x00000D22
 
@@ -4004,6 +4291,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_EVNT_SEL0            0x00000D30
 
@@ -4022,6 +4310,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_CTR0                 0x00000D31
 
@@ -4040,6 +4329,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_EVNT_SEL1            0x00000D32
 
@@ -4058,6 +4348,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_CTR1                 0x00000D33
 
@@ -4076,6 +4367,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_EVNT_SEL2            0x00000D34
 
@@ -4094,6 +4386,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_CTR2                 0x00000D35
 
@@ -4112,6 +4405,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_EVNT_SEL3            0x00000D36
 
@@ -4130,6 +4424,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_CTR3                 0x00000D37
 
@@ -4148,6 +4443,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_EVNT_SEL4            0x00000D38
 
@@ -4166,6 +4462,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_CTR4                 0x00000D39
 
@@ -4184,6 +4481,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_EVNT_SEL5            0x00000D3A
 
@@ -4202,6 +4500,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_C4_PMON_CTR5                 0x00000D3B
 
@@ -4220,6 +4519,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_BOX_CTRL             0x00000D40
 
@@ -4238,6 +4538,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_BOX_STATUS           0x00000D41
 
@@ -4256,6 +4557,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL         0x00000D42
 
@@ -4274,6 +4576,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_EVNT_SEL0            0x00000D50
 
@@ -4292,6 +4595,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_CTR0                 0x00000D51
 
@@ -4310,6 +4614,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_EVNT_SEL1            0x00000D52
 
@@ -4328,6 +4633,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_CTR1                 0x00000D53
 
@@ -4346,6 +4652,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_EVNT_SEL2            0x00000D54
 
@@ -4364,6 +4671,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_CTR2                 0x00000D55
 
@@ -4382,6 +4690,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_EVNT_SEL3            0x00000D56
 
@@ -4400,6 +4709,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_CTR3                 0x00000D57
 
@@ -4418,6 +4728,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_EVNT_SEL4            0x00000D58
 
@@ -4436,6 +4747,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_CTR4                 0x00000D59
 
@@ -4454,6 +4766,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_EVNT_SEL5            0x00000D5A
 
@@ -4472,6 +4785,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_C2_PMON_CTR5                 0x00000D5B
 
@@ -4490,6 +4804,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_BOX_CTRL             0x00000D60
 
@@ -4508,6 +4823,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_BOX_STATUS           0x00000D61
 
@@ -4526,6 +4842,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL         0x00000D62
 
@@ -4544,6 +4861,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_EVNT_SEL0            0x00000D70
 
@@ -4562,6 +4880,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_CTR0                 0x00000D71
 
@@ -4580,6 +4899,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_EVNT_SEL1            0x00000D72
 
@@ -4598,6 +4918,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_CTR1                 0x00000D73
 
@@ -4616,6 +4937,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_EVNT_SEL2            0x00000D74
 
@@ -4634,6 +4956,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_CTR2                 0x00000D75
 
@@ -4652,6 +4975,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_EVNT_SEL3            0x00000D76
 
@@ -4670,6 +4994,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_CTR3                 0x00000D77
 
@@ -4688,6 +5013,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_EVNT_SEL4            0x00000D78
 
@@ -4706,6 +5032,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_CTR4                 0x00000D79
 
@@ -4724,6 +5051,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_EVNT_SEL5            0x00000D7A
 
@@ -4742,6 +5070,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_C6_PMON_CTR5                 0x00000D7B
 
@@ -4760,6 +5089,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_BOX_CTRL             0x00000D80
 
@@ -4778,6 +5108,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_BOX_STATUS           0x00000D81
 
@@ -4796,6 +5127,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL         0x00000D82
 
@@ -4814,6 +5146,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_EVNT_SEL0            0x00000D90
 
@@ -4832,6 +5165,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_CTR0                 0x00000D91
 
@@ -4850,6 +5184,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_EVNT_SEL1            0x00000D92
 
@@ -4868,6 +5203,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_CTR1                 0x00000D93
 
@@ -4886,6 +5222,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_EVNT_SEL2            0x00000D94
 
@@ -4904,6 +5241,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_CTR2                 0x00000D95
 
@@ -4922,6 +5260,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_EVNT_SEL3            0x00000D96
 
@@ -4940,6 +5279,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_CTR3                 0x00000D97
 
@@ -4958,6 +5298,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_EVNT_SEL4            0x00000D98
 
@@ -4976,6 +5317,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_CTR4                 0x00000D99
 
@@ -4994,6 +5336,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_EVNT_SEL5            0x00000D9A
 
@@ -5012,6 +5355,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_C1_PMON_CTR5                 0x00000D9B
 
@@ -5030,6 +5374,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_BOX_CTRL             0x00000DA0
 
@@ -5048,6 +5393,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_BOX_STATUS           0x00000DA1
 
@@ -5066,6 +5412,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL         0x00000DA2
 
@@ -5084,6 +5431,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_EVNT_SEL0            0x00000DB0
 
@@ -5102,6 +5450,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_CTR0                 0x00000DB1
 
@@ -5120,6 +5469,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_EVNT_SEL1            0x00000DB2
 
@@ -5138,6 +5488,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_CTR1                 0x00000DB3
 
@@ -5156,6 +5507,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_EVNT_SEL2            0x00000DB4
 
@@ -5174,6 +5526,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_CTR2                 0x00000DB5
 
@@ -5192,6 +5545,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_EVNT_SEL3            0x00000DB6
 
@@ -5210,6 +5564,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_CTR3                 0x00000DB7
 
@@ -5228,6 +5583,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_EVNT_SEL4            0x00000DB8
 
@@ -5246,6 +5602,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_CTR4                 0x00000DB9
 
@@ -5264,6 +5621,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_EVNT_SEL5            0x00000DBA
 
@@ -5282,6 +5640,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_C5_PMON_CTR5                 0x00000DBB
 
@@ -5300,6 +5659,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_BOX_CTRL             0x00000DC0
 
@@ -5318,6 +5678,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_BOX_STATUS           0x00000DC1
 
@@ -5336,6 +5697,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL         0x00000DC2
 
@@ -5354,6 +5716,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_EVNT_SEL0            0x00000DD0
 
@@ -5372,6 +5735,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_CTR0                 0x00000DD1
 
@@ -5390,6 +5754,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_EVNT_SEL1            0x00000DD2
 
@@ -5408,6 +5773,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_CTR1                 0x00000DD3
 
@@ -5426,6 +5792,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_EVNT_SEL2            0x00000DD4
 
@@ -5444,6 +5811,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_CTR2                 0x00000DD5
 
@@ -5462,6 +5830,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_EVNT_SEL3            0x00000DD6
 
@@ -5480,6 +5849,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_CTR3                 0x00000DD7
 
@@ -5498,6 +5868,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_EVNT_SEL4            0x00000DD8
 
@@ -5516,6 +5887,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_CTR4                 0x00000DD9
 
@@ -5534,6 +5906,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_EVNT_SEL5            0x00000DDA
 
@@ -5552,6 +5925,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_C3_PMON_CTR5                 0x00000DDB
 
@@ -5570,6 +5944,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_BOX_CTRL             0x00000DE0
 
@@ -5588,6 +5963,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_BOX_STATUS           0x00000DE1
 
@@ -5606,6 +5982,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL         0x00000DE2
 
@@ -5624,6 +6001,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_EVNT_SEL0            0x00000DF0
 
@@ -5642,6 +6020,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_CTR0                 0x00000DF1
 
@@ -5660,6 +6039,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_EVNT_SEL1            0x00000DF2
 
@@ -5678,6 +6058,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_CTR1                 0x00000DF3
 
@@ -5696,6 +6077,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_EVNT_SEL2            0x00000DF4
 
@@ -5714,6 +6096,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_CTR2                 0x00000DF5
 
@@ -5732,6 +6115,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_EVNT_SEL3            0x00000DF6
 
@@ -5750,6 +6134,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_CTR3                 0x00000DF7
 
@@ -5768,6 +6153,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_EVNT_SEL4            0x00000DF8
 
@@ -5786,6 +6172,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_CTR4                 0x00000DF9
 
@@ -5804,6 +6191,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_EVNT_SEL5            0x00000DFA
 
@@ -5822,6 +6210,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_C7_PMON_CTR5                 0x00000DFB
 
@@ -5840,6 +6229,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_BOX_CTRL             0x00000E00
 
@@ -5858,6 +6248,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_BOX_STATUS           0x00000E01
 
@@ -5876,6 +6267,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL         0x00000E02
 
@@ -5894,6 +6286,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_IPERF0_P0            0x00000E04
 
@@ -5912,6 +6305,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_IPERF0_P1            0x00000E05
 
@@ -5930,6 +6324,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_IPERF0_P2            0x00000E06
 
@@ -5948,6 +6343,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_IPERF0_P3            0x00000E07
 
@@ -5966,6 +6362,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_IPERF0_P4            0x00000E08
 
@@ -5984,6 +6381,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_IPERF0_P5            0x00000E09
 
@@ -6002,6 +6400,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_IPERF0_P6            0x00000E0A
 
@@ -6020,6 +6419,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_IPERF0_P7            0x00000E0B
 
@@ -6038,6 +6438,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_QLX_P0               0x00000E0C
 
@@ -6056,6 +6457,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_QLX_P1               0x00000E0D
 
@@ -6074,6 +6476,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_QLX_P2               0x00000E0E
 
@@ -6092,6 +6495,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_QLX_P3               0x00000E0F
 
@@ -6110,6 +6514,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_EVNT_SEL0            0x00000E10
 
@@ -6128,6 +6533,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_CTR0                 0x00000E11
 
@@ -6146,6 +6552,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_EVNT_SEL1            0x00000E12
 
@@ -6164,6 +6571,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_CTR1                 0x00000E13
 
@@ -6182,6 +6590,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_EVNT_SEL2            0x00000E14
 
@@ -6200,6 +6609,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_CTR2                 0x00000E15
 
@@ -6218,6 +6628,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_EVNT_SEL3            0x00000E16
 
@@ -6236,6 +6647,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_CTR3                 0x00000E17
 
@@ -6254,6 +6666,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_EVNT_SEL4            0x00000E18
 
@@ -6272,6 +6685,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_CTR4                 0x00000E19
 
@@ -6290,6 +6704,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_EVNT_SEL5            0x00000E1A
 
@@ -6308,6 +6723,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_CTR5                 0x00000E1B
 
@@ -6326,6 +6742,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_EVNT_SEL6            0x00000E1C
 
@@ -6344,6 +6761,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_CTR6                 0x00000E1D
 
@@ -6362,6 +6780,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_EVNT_SEL7            0x00000E1E
 
@@ -6380,6 +6799,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);
   AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);
   @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.
 **/
 #define MSR_NEHALEM_R0_PMON_CTR7                 0x00000E1F
 
@@ -6398,6 +6818,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_BOX_CTRL             0x00000E20
 
@@ -6416,6 +6837,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_BOX_STATUS           0x00000E21
 
@@ -6434,6 +6856,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL         0x00000E22
 
@@ -6452,6 +6875,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_IPERF1_P8            0x00000E24
 
@@ -6470,6 +6894,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_IPERF1_P9            0x00000E25
 
@@ -6488,6 +6913,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_IPERF1_P10           0x00000E26
 
@@ -6506,6 +6932,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_IPERF1_P11           0x00000E27
 
@@ -6524,6 +6951,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_IPERF1_P12           0x00000E28
 
@@ -6542,6 +6970,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_IPERF1_P13           0x00000E29
 
@@ -6560,6 +6989,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_IPERF1_P14           0x00000E2A
 
@@ -6578,6 +7008,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_IPERF1_P15           0x00000E2B
 
@@ -6596,6 +7027,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_QLX_P4               0x00000E2C
 
@@ -6614,6 +7046,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_QLX_P5               0x00000E2D
 
@@ -6632,6 +7065,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_QLX_P6               0x00000E2E
 
@@ -6650,6 +7084,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_QLX_P7               0x00000E2F
 
@@ -6668,6 +7103,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_EVNT_SEL8            0x00000E30
 
@@ -6686,6 +7122,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_CTR8                 0x00000E31
 
@@ -6704,6 +7141,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_EVNT_SEL9            0x00000E32
 
@@ -6722,6 +7160,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_CTR9                 0x00000E33
 
@@ -6740,6 +7179,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_EVNT_SEL10           0x00000E34
 
@@ -6758,6 +7198,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_CTR10                0x00000E35
 
@@ -6776,6 +7217,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_EVNT_SEL11           0x00000E36
 
@@ -6794,6 +7236,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_CTR11                0x00000E37
 
@@ -6812,6 +7255,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_EVNT_SEL12           0x00000E38
 
@@ -6830,6 +7274,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_CTR12                0x00000E39
 
@@ -6848,6 +7293,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_EVNT_SEL13           0x00000E3A
 
@@ -6866,6 +7312,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_CTR13                0x00000E3B
 
@@ -6884,6 +7331,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_EVNT_SEL14           0x00000E3C
 
@@ -6902,6 +7350,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_CTR14                0x00000E3D
 
@@ -6920,6 +7369,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_EVNT_SEL15           0x00000E3E
 
@@ -6938,6 +7388,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);
   AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);
   @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.
 **/
 #define MSR_NEHALEM_R1_PMON_CTR15                0x00000E3F
 
@@ -6956,6 +7407,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_MATCH                0x00000E45
 
@@ -6974,6 +7426,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);
   AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);
   @endcode
+  @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.
 **/
 #define MSR_NEHALEM_B0_PMON_MASK                 0x00000E46
 
@@ -6992,6 +7445,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_MATCH                0x00000E49
 
@@ -7010,6 +7464,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);
   AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);
   @endcode
+  @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.
 **/
 #define MSR_NEHALEM_S0_PMON_MASK                 0x00000E4A
 
@@ -7028,6 +7483,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_MATCH                0x00000E4D
 
@@ -7046,6 +7502,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);
   AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);
   @endcode
+  @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.
 **/
 #define MSR_NEHALEM_B1_PMON_MASK                 0x00000E4E
 
@@ -7064,6 +7521,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_MM_CONFIG            0x00000E54
 
@@ -7082,6 +7540,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_ADDR_MATCH           0x00000E55
 
@@ -7100,6 +7559,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);
   AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);
   @endcode
+  @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.
 **/
 #define MSR_NEHALEM_M0_PMON_ADDR_MASK            0x00000E56
 
@@ -7118,6 +7578,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_MATCH                0x00000E59
 
@@ -7136,6 +7597,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);
   AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);
   @endcode
+  @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.
 **/
 #define MSR_NEHALEM_S1_PMON_MASK                 0x00000E5A
 
@@ -7154,6 +7616,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_MM_CONFIG            0x00000E5C
 
@@ -7172,6 +7635,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_ADDR_MATCH           0x00000E5D
 
@@ -7190,6 +7654,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);
   AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);
   @endcode
+  @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.
 **/
 #define MSR_NEHALEM_M1_PMON_ADDR_MASK            0x00000E5E
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 10/20] UefiCpuPkg/P6Msr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (8 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 09/20] UefiCpuPkg/NehalemMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 11/20] UefiCpuPkg/Pentium4Msr.h: " Jeff Fan
                   ` (9 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/P6Msr.h | 83 +++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
index 7ee0b28..a196330 100644
--- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
 **/
 #define MSR_P6_P5_MC_ADDR                        0x00000000
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
 **/
 #define MSR_P6_P5_MC_TYPE                        0x00000001
 
@@ -76,6 +78,7 @@
   Msr = AsmReadMsr64 (MSR_P6_TSC);
   AsmWriteMsr64 (MSR_P6_TSC, Msr);
   @endcode
+  @note MSR_P6_TSC is defined as TSC in SDM.
 **/
 #define MSR_P6_TSC                               0x00000010
 
@@ -96,6 +99,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
   @endcode
+  @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
 **/
 #define MSR_P6_IA32_PLATFORM_ID                  0x00000017
 
@@ -158,6 +162,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);
   AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);
   @endcode
+  @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.
 **/
 #define MSR_P6_APIC_BASE                         0x0000001B
 
@@ -214,6 +219,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.
 **/
 #define MSR_P6_EBL_CR_POWERON                    0x0000002A
 
@@ -338,6 +344,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);
   AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);
   @endcode
+  @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.
 **/
 #define MSR_P6_TEST_CTL                          0x00000033
 
@@ -385,6 +392,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);
   AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);
   @endcode
+  @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.
 **/
 #define MSR_P6_BIOS_UPDT_TRIG                    0x00000079
 
@@ -403,6 +411,9 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
   AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);
   @endcode
+  @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.
+        MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.
+        MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.
   @{
 **/
 #define MSR_P6_BBL_CR_D0                         0x00000088
@@ -426,6 +437,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);
   AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);
   @endcode
+  @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.
 **/
 #define MSR_P6_BIOS_SIGN                         0x0000008B
 
@@ -444,6 +456,8 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
   AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);
   @endcode
+  @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.
+        MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.
   @{
 **/
 #define MSR_P6_PERFCTR0                          0x000000C1
@@ -465,6 +479,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);
   AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);
   @endcode
+  @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.
 **/
 #define MSR_P6_MTRRCAP                           0x000000FE
 
@@ -486,6 +501,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);
   AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);
   @endcode
+  @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.
 **/
 #define MSR_P6_BBL_CR_ADDR                       0x00000116
 
@@ -529,6 +545,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);
   AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);
   @endcode
+  @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.
 **/
 #define MSR_P6_BBL_CR_DECC                       0x00000118
 
@@ -550,6 +567,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);
   AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);
   @endcode
+  @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.
 **/
 #define MSR_P6_BBL_CR_CTL                        0x00000119
 
@@ -637,6 +655,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);
   AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);
   @endcode
+  @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.
 **/
 #define MSR_P6_BBL_CR_TRIG                       0x0000011A
 
@@ -656,6 +675,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);
   AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);
   @endcode
+  @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.
 **/
 #define MSR_P6_BBL_CR_BUSY                       0x0000011B
 
@@ -676,6 +696,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.
 **/
 #define MSR_P6_BBL_CR_CTL3                       0x0000011E
 
@@ -772,6 +793,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);
   AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);
   @endcode
+  @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.
 **/
 #define MSR_P6_SYSENTER_CS_MSR                   0x00000174
 
@@ -790,6 +812,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);
   AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);
   @endcode
+  @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.
 **/
 #define MSR_P6_SYSENTER_ESP_MSR                  0x00000175
 
@@ -808,6 +831,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);
   AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);
   @endcode
+  @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.
 **/
 #define MSR_P6_SYSENTER_EIP_MSR                  0x00000176
 
@@ -826,6 +850,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);
   AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);
   @endcode
+  @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.
 **/
 #define MSR_P6_MCG_CAP                           0x00000179
 
@@ -844,6 +869,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);
   AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);
   @endcode
+  @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.
 **/
 #define MSR_P6_MCG_STATUS                        0x0000017A
 
@@ -862,6 +888,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);
   AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);
   @endcode
+  @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.
 **/
 #define MSR_P6_MCG_CTL                           0x0000017B
 
@@ -882,6 +909,8 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);
   @endcode
+  @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM.
+        MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.
   @{
 **/
 #define MSR_P6_PERFEVTSEL0                       0x00000186
@@ -974,6 +1003,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);
   AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);
   @endcode
+  @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.
 **/
 #define MSR_P6_DEBUGCTLMSR                       0x000001D9
 
@@ -1041,6 +1071,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);
   AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);
   @endcode
+  @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.
 **/
 #define MSR_P6_LASTBRANCHFROMIP                  0x000001DB
 
@@ -1059,6 +1090,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);
   AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);
   @endcode
+  @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.
 **/
 #define MSR_P6_LASTBRANCHTOIP                    0x000001DC
 
@@ -1077,6 +1109,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);
   AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);
   @endcode
+  @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.
 **/
 #define MSR_P6_LASTINTFROMIP                     0x000001DD
 
@@ -1095,6 +1128,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);
   AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);
   @endcode
+  @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.
 **/
 #define MSR_P6_LASTINTTOIP                       0x000001DE
 
@@ -1115,6 +1149,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6);
   AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64);
   @endcode
+  @note MSR_P6_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
 **/
 #define MSR_P6_ROB_CR_BKUPTMPDR6                 0x000001E0
 
@@ -1159,6 +1194,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
   AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);
   @endcode
+  @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
+        MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
+        MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
+        MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
+        MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
+        MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
+        MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
+        MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
   @{
 **/
 #define MSR_P6_MTRRPHYSBASE0                     0x00000200
@@ -1186,6 +1229,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
   AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);
   @endcode
+  @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
+        MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
+        MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
+        MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
+        MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
+        MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
+        MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
+        MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
   @{
 **/
 #define MSR_P6_MTRRPHYSMASK0                     0x00000201
@@ -1213,6 +1264,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
 **/
 #define MSR_P6_MTRRFIX64K_00000                  0x00000250
 
@@ -1231,6 +1283,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
 **/
 #define MSR_P6_MTRRFIX16K_80000                  0x00000258
 
@@ -1249,6 +1302,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
 **/
 #define MSR_P6_MTRRFIX16K_A0000                  0x00000259
 
@@ -1267,6 +1321,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
 **/
 #define MSR_P6_MTRRFIX4K_C0000                   0x00000268
 
@@ -1285,6 +1340,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
 **/
 #define MSR_P6_MTRRFIX4K_C8000                   0x00000269
 
@@ -1303,6 +1359,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
 **/
 #define MSR_P6_MTRRFIX4K_D0000                   0x0000026A
 
@@ -1321,6 +1378,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
 **/
 #define MSR_P6_MTRRFIX4K_D8000                   0x0000026B
 
@@ -1339,6 +1397,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
 **/
 #define MSR_P6_MTRRFIX4K_E0000                   0x0000026C
 
@@ -1357,6 +1416,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
 **/
 #define MSR_P6_MTRRFIX4K_E8000                   0x0000026D
 
@@ -1375,6 +1435,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
 **/
 #define MSR_P6_MTRRFIX4K_F0000                   0x0000026E
 
@@ -1393,6 +1454,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);
   AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);
   @endcode
+  @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
 **/
 #define MSR_P6_MTRRFIX4K_F8000                   0x0000026F
 
@@ -1413,6 +1475,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);
   AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);
   @endcode
+  @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.
 **/
 #define MSR_P6_MTRRDEFTYPE                       0x000002FF
 
@@ -1465,6 +1528,11 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
   AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);
   @endcode
+  @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM.
+        MSR_P6_MC1_CTL is defined as MC1_CTL in SDM.
+        MSR_P6_MC2_CTL is defined as MC2_CTL in SDM.
+        MSR_P6_MC3_CTL is defined as MC3_CTL in SDM.
+        MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.
   @{
 **/
 #define MSR_P6_MC0_CTL                           0x00000400
@@ -1493,6 +1561,11 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
   AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM.
+        MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM.
+        MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM.
+        MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM.
+        MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.
   @{
 **/
 #define MSR_P6_MC0_STATUS                        0x00000401
@@ -1572,6 +1645,11 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
   AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);
   @endcode
+  @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM.
+        MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM.
+        MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM.
+        MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM.
+        MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.
   @{
 **/
 #define MSR_P6_MC0_ADDR                          0x00000402
@@ -1596,6 +1674,11 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
   AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);
   @endcode
+  @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM.
+        MSR_P6_MC1_MISC is defined as MC1_MISC in SDM.
+        MSR_P6_MC2_MISC is defined as MC2_MISC in SDM.
+        MSR_P6_MC3_MISC is defined as MC3_MISC in SDM.
+        MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.
   @{
 **/
 #define MSR_P6_MC0_MISC                          0x00000403
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 11/20] UefiCpuPkg/Pentium4Msr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (9 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 10/20] UefiCpuPkg/P6Msr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 12/20] UefiCpuPkg/PentiumMMsr.h: " Jeff Fan
                   ` (8 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 167 ++++++++++++++++++++++++++
 1 file changed, 167 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
index caeb5bb..306857f 100644
--- a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
@@ -41,6 +41,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);
   AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.
 **/
 #define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006
 
@@ -63,6 +64,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);
   AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.
 **/
 #define MSR_PENTIUM_4_EBC_HARD_POWERON           0x0000002A
 
@@ -162,6 +164,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);
   AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.
 **/
 #define MSR_PENTIUM_4_EBC_SOFT_POWERON           0x0000002B
 
@@ -242,6 +245,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);
   @endcode
+  @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.
 **/
 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID           0x0000002C
 
@@ -314,6 +318,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);
   @endcode
+  @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.
 **/
 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1         0x0000002C
 
@@ -364,6 +369,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RAX                    0x00000180
 
@@ -385,6 +391,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RBX                    0x00000181
 
@@ -406,6 +413,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RCX                    0x00000182
 
@@ -427,6 +435,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RDX                    0x00000183
 
@@ -448,6 +457,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RSI                    0x00000184
 
@@ -469,6 +479,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RDI                    0x00000185
 
@@ -490,6 +501,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RBP                    0x00000186
 
@@ -511,6 +523,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RSP                    0x00000187
 
@@ -532,6 +545,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RFLAGS                 0x00000188
 
@@ -553,6 +567,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_RIP                    0x00000189
 
@@ -574,6 +589,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_MISC                   0x0000018A
 
@@ -625,6 +641,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_R8                     0x00000190
 
@@ -647,6 +664,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_R9                     0x00000191
 
@@ -669,6 +687,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_R10                    0x00000192
 
@@ -691,6 +710,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_R11                    0x00000193
 
@@ -713,6 +733,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_R12                    0x00000194
 
@@ -735,6 +756,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_R13                    0x00000195
 
@@ -757,6 +779,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_R14                    0x00000196
 
@@ -779,6 +802,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);
   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.
 **/
 #define MSR_PENTIUM_4_MCG_R15                    0x00000197
 
@@ -801,6 +825,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);
   AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);
   @endcode
+  @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 **/
 #define MSR_PENTIUM_4_THERM2_CTL                 0x0000019D
 
@@ -821,6 +846,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_PENTIUM_4_IA32_MISC_ENABLE           0x000001A0
 
@@ -990,6 +1016,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);
   @endcode
+  @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.
 **/
 #define MSR_PENTIUM_4_PLATFORM_BRV               0x000001A1
 
@@ -1040,6 +1067,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);
   @endcode
+  @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_PENTIUM_4_LER_FROM_LIP               0x000001D7
 
@@ -1063,6 +1091,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);
   @endcode
+  @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_PENTIUM_4_LER_TO_LIP                 0x000001D8
 
@@ -1083,6 +1112,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);
   AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);
   @endcode
+  @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.
 **/
 #define MSR_PENTIUM_4_DEBUGCTLA                  0x000001D9
 
@@ -1105,6 +1135,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_PENTIUM_4_LASTBRANCH_TOS             0x000001DA
 
@@ -1130,6 +1161,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);
   AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_LASTBRANCH_0               0x000001DB
@@ -1153,6 +1188,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);
   AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM.
+        MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM.
+        MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM.
+        MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_BPU_COUNTER0               0x00000300
@@ -1176,6 +1215,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);
   AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM.
+        MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM.
+        MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM.
+        MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_MS_COUNTER0                0x00000304
@@ -1199,6 +1242,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);
   AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM.
+        MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM.
+        MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM.
+        MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_FLAME_COUNTER0             0x00000308
@@ -1222,6 +1269,12 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
   AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM.
+        MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM.
+        MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM.
+        MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM.
+        MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM.
+        MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_IQ_COUNTER0                0x0000030C
@@ -1247,6 +1300,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM.
+        MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM.
+        MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM.
+        MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_BPU_CCCR0                  0x00000360
@@ -1270,6 +1327,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM.
+        MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM.
+        MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM.
+        MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_MS_CCCR0                   0x00000364
@@ -1293,6 +1354,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM.
+        MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM.
+        MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM.
+        MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_FLAME_CCCR0                0x00000368
@@ -1316,6 +1381,12 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM.
+        MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM.
+        MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM.
+        MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM.
+        MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM.
+        MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_IQ_CCCR0                   0x0000036C
@@ -1341,6 +1412,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_BSU_ESCR0                  0x000003A0
 
@@ -1359,6 +1431,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_BSU_ESCR1                  0x000003A1
 
@@ -1377,6 +1450,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_FSB_ESCR0                  0x000003A2
 
@@ -1395,6 +1469,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_FSB_ESCR1                  0x000003A3
 
@@ -1413,6 +1488,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_FIRM_ESCR0                 0x000003A4
 
@@ -1431,6 +1507,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_FIRM_ESCR1                 0x000003A5
 
@@ -1449,6 +1526,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_FLAME_ESCR0                0x000003A6
 
@@ -1467,6 +1545,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_FLAME_ESCR1                0x000003A7
 
@@ -1485,6 +1564,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_DAC_ESCR0                  0x000003A8
 
@@ -1503,6 +1583,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_DAC_ESCR1                  0x000003A9
 
@@ -1521,6 +1602,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_MOB_ESCR0                  0x000003AA
 
@@ -1539,6 +1621,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_MOB_ESCR1                  0x000003AB
 
@@ -1557,6 +1640,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_PMH_ESCR0                  0x000003AC
 
@@ -1575,6 +1659,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_PMH_ESCR1                  0x000003AD
 
@@ -1593,6 +1678,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_SAAT_ESCR0                 0x000003AE
 
@@ -1611,6 +1697,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_SAAT_ESCR1                 0x000003AF
 
@@ -1629,6 +1716,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_U2L_ESCR0                  0x000003B0
 
@@ -1647,6 +1735,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_U2L_ESCR1                  0x000003B1
 
@@ -1665,6 +1754,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_BPU_ESCR0                  0x000003B2
 
@@ -1683,6 +1773,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_BPU_ESCR1                  0x000003B3
 
@@ -1701,6 +1792,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_IS_ESCR0                   0x000003B4
 
@@ -1719,6 +1811,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_IS_ESCR1                   0x000003B5
 
@@ -1737,6 +1830,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_ITLB_ESCR0                 0x000003B6
 
@@ -1755,6 +1849,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_ITLB_ESCR1                 0x000003B7
 
@@ -1773,6 +1868,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_CRU_ESCR0                  0x000003B8
 
@@ -1791,6 +1887,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_CRU_ESCR1                  0x000003B9
 
@@ -1811,6 +1908,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_IQ_ESCR0                   0x000003BA
 
@@ -1831,6 +1929,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_IQ_ESCR1                   0x000003BB
 
@@ -1849,6 +1948,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_RAT_ESCR0                  0x000003BC
 
@@ -1867,6 +1967,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_RAT_ESCR1                  0x000003BD
 
@@ -1885,6 +1986,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_SSU_ESCR0                  0x000003BE
 
@@ -1903,6 +2005,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_MS_ESCR0                   0x000003C0
 
@@ -1921,6 +2024,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_MS_ESCR1                   0x000003C1
 
@@ -1939,6 +2043,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_TBPU_ESCR0                 0x000003C2
 
@@ -1957,6 +2062,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_TBPU_ESCR1                 0x000003C3
 
@@ -1975,6 +2081,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_TC_ESCR0                   0x000003C4
 
@@ -1993,6 +2100,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_TC_ESCR1                   0x000003C5
 
@@ -2011,6 +2119,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.
 **/
 #define MSR_PENTIUM_4_IX_ESCR0                   0x000003C8
 
@@ -2029,6 +2138,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);
   AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.
 **/
 #define MSR_PENTIUM_4_IX_ESCR1                   0x000003C9
 
@@ -2047,6 +2157,12 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
   AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM.
+        MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM.
+        MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM.
+        MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM.
+        MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM.
+        MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_ALF_ESCR0                  0x000003CA
@@ -2072,6 +2188,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);
   AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);
   @endcode
+  @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.
 **/
 #define MSR_PENTIUM_4_TC_PRECISE_EVENT           0x000003F0
 
@@ -2093,6 +2210,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);
   AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
 **/
 #define MSR_PENTIUM_4_PEBS_ENABLE                0x000003F1
 
@@ -2157,6 +2275,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);
   AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);
   @endcode
+  @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.
 **/
 #define MSR_PENTIUM_4_PEBS_MATRIX_VERT           0x000003F2
 
@@ -2183,6 +2302,22 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
   AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);
   @endcode
+  @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP  is defined as MSR_LASTBRANCH_0_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP  is defined as MSR_LASTBRANCH_1_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP  is defined as MSR_LASTBRANCH_2_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP  is defined as MSR_LASTBRANCH_3_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP  is defined as MSR_LASTBRANCH_4_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP  is defined as MSR_LASTBRANCH_5_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP  is defined as MSR_LASTBRANCH_6_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP  is defined as MSR_LASTBRANCH_7_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP  is defined as MSR_LASTBRANCH_8_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP  is defined as MSR_LASTBRANCH_9_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP       0x00000680
@@ -2223,6 +2358,22 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
   AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);
   @endcode
+  @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP  is defined as MSR_LASTBRANCH_0_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_1_TO_IP  is defined as MSR_LASTBRANCH_1_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_2_TO_IP  is defined as MSR_LASTBRANCH_2_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_3_TO_IP  is defined as MSR_LASTBRANCH_3_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_4_TO_IP  is defined as MSR_LASTBRANCH_4_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_5_TO_IP  is defined as MSR_LASTBRANCH_5_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_6_TO_IP  is defined as MSR_LASTBRANCH_6_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_7_TO_IP  is defined as MSR_LASTBRANCH_7_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_8_TO_IP  is defined as MSR_LASTBRANCH_8_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_9_TO_IP  is defined as MSR_LASTBRANCH_9_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
   @{
 **/
 #define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP         0x000006C0
@@ -2260,6 +2411,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);
   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.
 **/
 #define MSR_PENTIUM_4_IFSB_BUSQ0                 0x000107CC
 
@@ -2278,6 +2430,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);
   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.
 **/
 #define MSR_PENTIUM_4_IFSB_BUSQ1                 0x000107CD
 
@@ -2298,6 +2451,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);
   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.
 **/
 #define MSR_PENTIUM_4_IFSB_SNPQ0                 0x000107CE
 
@@ -2316,6 +2470,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);
   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.
 **/
 #define MSR_PENTIUM_4_IFSB_SNPQ1                 0x000107CF
 
@@ -2336,6 +2491,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);
   AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.
 **/
 #define MSR_PENTIUM_4_EFSB_DRDY0                 0x000107D0
 
@@ -2354,6 +2510,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);
   AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.
 **/
 #define MSR_PENTIUM_4_EFSB_DRDY1                 0x000107D1
 
@@ -2374,6 +2531,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);
   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.
 **/
 #define MSR_PENTIUM_4_IFSB_CTL6                  0x000107D2
 
@@ -2394,6 +2552,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);
   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);
   @endcode
+  @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.
 **/
 #define MSR_PENTIUM_4_IFSB_CNTR7                 0x000107D3
 
@@ -2414,6 +2573,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);
   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);
   @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
 **/
 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL0           0x000107CC
 
@@ -2432,6 +2592,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);
   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);
   @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
 **/
 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL1           0x000107CD
 
@@ -2452,6 +2613,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);
   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);
   @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
 **/
 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL2           0x000107CE
 
@@ -2470,6 +2632,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);
   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);
   @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
 **/
 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL3           0x000107CF
 
@@ -2490,6 +2653,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);
   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);
   @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
 **/
 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL4           0x000107D0
 
@@ -2508,6 +2672,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);
   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);
   @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
 **/
 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL5           0x000107D1
 
@@ -2526,6 +2691,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);
   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);
   @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
 **/
 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL6           0x000107D2
 
@@ -2544,6 +2710,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);
   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);
   @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
 **/
 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL7           0x000107D3
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 12/20] UefiCpuPkg/PentiumMMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (10 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 11/20] UefiCpuPkg/Pentium4Msr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 13/20] UefiCpuPkg/PentiumMsr.h: " Jeff Fan
                   ` (7 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
index 324fc9b..3040631 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
 **/
 #define MSR_PENTIUM_M_P5_MC_ADDR                 0x00000000
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
 **/
 #define MSR_PENTIUM_M_P5_MC_TYPE                 0x00000001
 
@@ -79,6 +81,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_PENTIUM_M_EBL_CR_POWERON             0x0000002A
 
@@ -195,6 +198,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
   AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
   @endcode
+  @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
   @{
 **/
 #define MSR_PENTIUM_M_LASTBRANCH_0               0x00000040
@@ -222,6 +233,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
   AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
   @endcode
+  @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
 **/
 #define MSR_PENTIUM_M_BBL_CR_CTL                 0x00000119
 
@@ -242,6 +254,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_PENTIUM_M_BBL_CR_CTL3                0x0000011E
 
@@ -308,6 +321,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
   AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 **/
 #define MSR_PENTIUM_M_THERM2_CTL                 0x0000019D
 
@@ -359,6 +373,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_PENTIUM_M_IA32_MISC_ENABLE           0x000001A0
 
@@ -460,6 +475,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_PENTIUM_M_LASTBRANCH_TOS             0x000001C9
 
@@ -480,6 +496,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
   AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
   @endcode
+  @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
 **/
 #define MSR_PENTIUM_M_DEBUGCTLB                  0x000001D9
 
@@ -502,6 +519,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
   @endcode
+  @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_PENTIUM_M_LER_TO_LIP                 0x000001DD
 
@@ -523,6 +541,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
   @endcode
+  @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_PENTIUM_M_LER_FROM_LIP               0x000001DE
 
@@ -541,6 +560,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
   AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
   @endcode
+  @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
 **/
 #define MSR_PENTIUM_M_MC4_CTL                    0x0000040C
 
@@ -559,6 +579,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
   AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
   @endcode
+  @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
 **/
 #define MSR_PENTIUM_M_MC4_STATUS                 0x0000040D
 
@@ -580,6 +601,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
   AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
   @endcode
+  @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
 **/
 #define MSR_PENTIUM_M_MC4_ADDR                   0x0000040E
 
@@ -598,6 +620,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
   AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
   @endcode
+  @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
 **/
 #define MSR_PENTIUM_M_MC3_CTL                    0x00000410
 
@@ -616,6 +639,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
   AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
   @endcode
+  @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
 **/
 #define MSR_PENTIUM_M_MC3_STATUS                 0x00000411
 
@@ -637,6 +661,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
   AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
   @endcode
+  @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
 **/
 #define MSR_PENTIUM_M_MC3_ADDR                   0x00000412
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 13/20] UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (11 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 12/20] UefiCpuPkg/PentiumMMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 14/20] UefiCpuPkg/SandyBridgeMsr.h: " Jeff Fan
                   ` (6 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
index a8916b4..62c5b7e 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
   @endcode
+  @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
 **/
 #define MSR_PENTIUM_P5_MC_ADDR                   0x00000000
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
   @endcode
+  @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
 **/
 #define MSR_PENTIUM_P5_MC_TYPE                   0x00000001
 
@@ -76,6 +78,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
   AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
   @endcode
+  @note MSR_PENTIUM_TSC is defined as TSC in SDM.
 **/
 #define MSR_PENTIUM_TSC                          0x00000010
 
@@ -94,6 +97,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
   AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
   @endcode
+  @note MSR_PENTIUM_CESR is defined as CESR in SDM.
 **/
 #define MSR_PENTIUM_CESR                         0x00000011
 
@@ -112,6 +116,8 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
   AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
   @endcode
+  @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
+        MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
   @{
 **/
 #define MSR_PENTIUM_CTR0                         0x00000012
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 14/20] UefiCpuPkg/SandyBridgeMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (12 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 13/20] UefiCpuPkg/PentiumMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 15/20] UefiCpuPkg/SilvermontMsr.h: " Jeff Fan
                   ` (5 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 271 +++++++++++++++++++++++
 1 file changed, 271 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
index c41e45b..a50bad2 100644
--- a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
   @endcode
+  @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_SMI_COUNT               0x00000034
 
@@ -85,6 +86,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PLATFORM_INFO           0x000000CE
 
@@ -153,6 +155,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL  0x000000E2
 
@@ -242,6 +245,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE     0x000000E4
 
@@ -301,6 +305,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
 **/
 #define MSR_SANDY_BRIDGE_FEATURE_CONFIG          0x0000013C
 
@@ -350,6 +355,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.
+        MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.
+        MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.
+        MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.
   @{
 **/
 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4        0x0000018A
@@ -375,6 +384,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PERF_STATUS             0x00000198
 
@@ -418,6 +428,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
 **/
 #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION   0x0000019A
 
@@ -470,6 +481,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE        0x000001A0
 
@@ -564,6 +576,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
 **/
 #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET      0x000001A2
 
@@ -611,6 +624,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL    0x000001A4
 
@@ -675,6 +689,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0           0x000001A6
 
@@ -693,6 +708,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_1           0x000001A7
 
@@ -711,6 +727,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_MISC_PWR_MGMT           0x000001AA
 
@@ -732,6 +749,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_LBR_SELECT              0x000001C8
 
@@ -809,6 +827,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_LASTBRANCH_TOS          0x000001C9
 
@@ -828,6 +847,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);
   @endcode
+  @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_SANDY_BRIDGE_LER_FROM_LIP            0x000001DD
 
@@ -848,6 +868,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);
   @endcode
+  @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_SANDY_BRIDGE_LER_TO_LIP              0x000001DE
 
@@ -866,6 +887,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_POWER_CTL               0x000001FC
 
@@ -884,6 +906,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_MC4_CTL2 is defined as MSR_MC4_CTL2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_MC4_CTL2                0x00000284
 
@@ -904,6 +927,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS  0x0000038E
 
@@ -999,6 +1023,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL   0x0000038F
 
@@ -1085,6 +1110,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
 
@@ -1179,6 +1205,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PEBS_ENABLE             0x000003F1
 
@@ -1253,6 +1280,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PEBS_LD_LAT             0x000003F6
 
@@ -1300,6 +1328,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY        0x000003F8
 
@@ -1321,6 +1350,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY        0x000003F9
 
@@ -1342,6 +1372,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY        0x000003FA
 
@@ -1363,6 +1394,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
 **/
 #define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY       0x000003FC
 
@@ -1384,6 +1416,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
 **/
 #define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY       0x000003FD
 
@@ -1405,6 +1438,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.
 **/
 #define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY       0x000003FE
 
@@ -1425,6 +1459,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_MC4_CTL                 0x00000410
 
@@ -1478,6 +1513,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);
   @endcode
+  @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
 **/
 #define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM  0x0000048C
 
@@ -1496,6 +1532,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);
   @endcode
+  @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT         0x00000606
 
@@ -1518,6 +1555,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKGC3_IRTL              0x0000060A
 
@@ -1583,6 +1621,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKGC6_IRTL              0x0000060B
 
@@ -1644,6 +1683,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY        0x0000060D
 
@@ -1663,6 +1703,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT         0x00000610
 
@@ -1680,6 +1721,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS       0x00000611
 
@@ -1699,6 +1741,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKG_POWER_INFO          0x00000614
 
@@ -1718,6 +1761,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT         0x00000638
 
@@ -1736,6 +1780,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);
   @endcode
+  @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS       0x00000639
 
@@ -1757,6 +1802,22 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP  is defined as MSR_LASTBRANCH_0_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP  is defined as MSR_LASTBRANCH_1_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP  is defined as MSR_LASTBRANCH_2_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP  is defined as MSR_LASTBRANCH_3_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP  is defined as MSR_LASTBRANCH_4_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP  is defined as MSR_LASTBRANCH_5_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP  is defined as MSR_LASTBRANCH_6_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP  is defined as MSR_LASTBRANCH_7_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP  is defined as MSR_LASTBRANCH_8_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP  is defined as MSR_LASTBRANCH_9_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
   @{
 **/
 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP    0x00000680
@@ -1794,6 +1855,22 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP  is defined as MSR_LASTBRANCH_0_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP  is defined as MSR_LASTBRANCH_1_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP  is defined as MSR_LASTBRANCH_2_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP  is defined as MSR_LASTBRANCH_3_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP  is defined as MSR_LASTBRANCH_4_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP  is defined as MSR_LASTBRANCH_5_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP  is defined as MSR_LASTBRANCH_6_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP  is defined as MSR_LASTBRANCH_7_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP  is defined as MSR_LASTBRANCH_8_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP  is defined as MSR_LASTBRANCH_9_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
   @{
 **/
 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP      0x000006C0
@@ -1831,6 +1908,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT       0x000001AD
 
@@ -1906,6 +1984,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL    0x00000391
 
@@ -1976,6 +2055,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS  0x00000392
 
@@ -2031,6 +2111,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL     0x00000394
 
@@ -2082,6 +2163,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR      0x00000395
 
@@ -2125,6 +2207,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG          0x00000396
 
@@ -2168,6 +2251,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0        0x000003B0
 
@@ -2186,6 +2270,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1        0x000003B1
 
@@ -2204,6 +2289,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0     0x000003B2
 
@@ -2222,6 +2308,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1     0x000003B3
 
@@ -2247,6 +2334,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKGC7_IRTL              0x0000060C
 
@@ -2306,6 +2394,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PP0_POLICY              0x0000063A
 
@@ -2325,6 +2414,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT         0x00000640
 
@@ -2343,6 +2433,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);
   @endcode
+  @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS       0x00000641
 
@@ -2362,6 +2453,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PP1_POLICY              0x00000642
 
@@ -2380,6 +2472,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0   0x00000700
 
@@ -2398,6 +2491,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1   0x00000701
 
@@ -2416,6 +2510,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0      0x00000706
 
@@ -2434,6 +2529,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1      0x00000707
 
@@ -2452,6 +2548,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0   0x00000710
 
@@ -2470,6 +2567,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1   0x00000711
 
@@ -2488,6 +2586,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0      0x00000716
 
@@ -2506,6 +2605,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1      0x00000717
 
@@ -2524,6 +2624,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0   0x00000720
 
@@ -2542,6 +2643,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1   0x00000721
 
@@ -2560,6 +2662,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0      0x00000726
 
@@ -2578,6 +2681,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1      0x00000727
 
@@ -2596,6 +2700,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0   0x00000730
 
@@ -2614,6 +2719,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1   0x00000731
 
@@ -2632,6 +2738,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0      0x00000736
 
@@ -2650,6 +2757,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1      0x00000737
 
@@ -2670,6 +2778,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_ERROR_CONTROL           0x0000017F
 
@@ -2717,6 +2826,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);
   @endcode
+  @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PEBS_NUM_ALT            0x0000039C
 
@@ -2762,6 +2872,21 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_MC5_CTL  is defined as MSR_MC5_CTL  in SDM.
+        MSR_SANDY_BRIDGE_MC6_CTL  is defined as MSR_MC6_CTL  in SDM.
+        MSR_SANDY_BRIDGE_MC7_CTL  is defined as MSR_MC7_CTL  in SDM.
+        MSR_SANDY_BRIDGE_MC8_CTL  is defined as MSR_MC8_CTL  in SDM.
+        MSR_SANDY_BRIDGE_MC9_CTL  is defined as MSR_MC9_CTL  in SDM.
+        MSR_SANDY_BRIDGE_MC10_CTL is defined as MSR_MC10_CTL in SDM.
+        MSR_SANDY_BRIDGE_MC11_CTL is defined as MSR_MC11_CTL in SDM.
+        MSR_SANDY_BRIDGE_MC12_CTL is defined as MSR_MC12_CTL in SDM.
+        MSR_SANDY_BRIDGE_MC13_CTL is defined as MSR_MC13_CTL in SDM.
+        MSR_SANDY_BRIDGE_MC14_CTL is defined as MSR_MC14_CTL in SDM.
+        MSR_SANDY_BRIDGE_MC15_CTL is defined as MSR_MC15_CTL in SDM.
+        MSR_SANDY_BRIDGE_MC16_CTL is defined as MSR_MC16_CTL in SDM.
+        MSR_SANDY_BRIDGE_MC17_CTL is defined as MSR_MC17_CTL in SDM.
+        MSR_SANDY_BRIDGE_MC18_CTL is defined as MSR_MC18_CTL in SDM.
+        MSR_SANDY_BRIDGE_MC19_CTL is defined as MSR_MC19_CTL in SDM.
   @{
 **/
 #define MSR_SANDY_BRIDGE_MC5_CTL                 0x00000414
@@ -2796,6 +2921,21 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_MC5_STATUS  is defined as MSR_MC5_STATUS  in SDM.
+        MSR_SANDY_BRIDGE_MC6_STATUS  is defined as MSR_MC6_STATUS  in SDM.
+        MSR_SANDY_BRIDGE_MC7_STATUS  is defined as MSR_MC7_STATUS  in SDM.
+        MSR_SANDY_BRIDGE_MC8_STATUS  is defined as MSR_MC8_STATUS  in SDM.
+        MSR_SANDY_BRIDGE_MC9_STATUS  is defined as MSR_MC9_STATUS  in SDM.
+        MSR_SANDY_BRIDGE_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
+        MSR_SANDY_BRIDGE_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
+        MSR_SANDY_BRIDGE_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
+        MSR_SANDY_BRIDGE_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
+        MSR_SANDY_BRIDGE_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
+        MSR_SANDY_BRIDGE_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
+        MSR_SANDY_BRIDGE_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
+        MSR_SANDY_BRIDGE_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
+        MSR_SANDY_BRIDGE_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
+        MSR_SANDY_BRIDGE_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
   @{
 **/
 #define MSR_SANDY_BRIDGE_MC5_STATUS              0x00000415
@@ -2830,6 +2970,21 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_MC5_ADDR  is defined as MSR_MC5_ADDR  in SDM.
+        MSR_SANDY_BRIDGE_MC6_ADDR  is defined as MSR_MC6_ADDR  in SDM.
+        MSR_SANDY_BRIDGE_MC7_ADDR  is defined as MSR_MC7_ADDR  in SDM.
+        MSR_SANDY_BRIDGE_MC8_ADDR  is defined as MSR_MC8_ADDR  in SDM.
+        MSR_SANDY_BRIDGE_MC9_ADDR  is defined as MSR_MC9_ADDR  in SDM.
+        MSR_SANDY_BRIDGE_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
+        MSR_SANDY_BRIDGE_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
+        MSR_SANDY_BRIDGE_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
+        MSR_SANDY_BRIDGE_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
+        MSR_SANDY_BRIDGE_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
+        MSR_SANDY_BRIDGE_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
+        MSR_SANDY_BRIDGE_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
+        MSR_SANDY_BRIDGE_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
+        MSR_SANDY_BRIDGE_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
+        MSR_SANDY_BRIDGE_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
   @{
 **/
 #define MSR_SANDY_BRIDGE_MC5_ADDR                0x00000416
@@ -2864,6 +3019,21 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_MISC);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_MISC, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_MC5_MISC  is defined as MSR_MC5_MISC  in SDM.
+        MSR_SANDY_BRIDGE_MC6_MISC  is defined as MSR_MC6_MISC  in SDM.
+        MSR_SANDY_BRIDGE_MC7_MISC  is defined as MSR_MC7_MISC  in SDM.
+        MSR_SANDY_BRIDGE_MC8_MISC  is defined as MSR_MC8_MISC  in SDM.
+        MSR_SANDY_BRIDGE_MC9_MISC  is defined as MSR_MC9_MISC  in SDM.
+        MSR_SANDY_BRIDGE_MC10_MISC is defined as MSR_MC10_MISC in SDM.
+        MSR_SANDY_BRIDGE_MC11_MISC is defined as MSR_MC11_MISC in SDM.
+        MSR_SANDY_BRIDGE_MC12_MISC is defined as MSR_MC12_MISC in SDM.
+        MSR_SANDY_BRIDGE_MC13_MISC is defined as MSR_MC13_MISC in SDM.
+        MSR_SANDY_BRIDGE_MC14_MISC is defined as MSR_MC14_MISC in SDM.
+        MSR_SANDY_BRIDGE_MC15_MISC is defined as MSR_MC15_MISC in SDM.
+        MSR_SANDY_BRIDGE_MC16_MISC is defined as MSR_MC16_MISC in SDM.
+        MSR_SANDY_BRIDGE_MC17_MISC is defined as MSR_MC17_MISC in SDM.
+        MSR_SANDY_BRIDGE_MC18_MISC is defined as MSR_MC18_MISC in SDM.
+        MSR_SANDY_BRIDGE_MC19_MISC is defined as MSR_MC19_MISC in SDM.
   @{
 **/
 #define MSR_SANDY_BRIDGE_MC5_MISC                0x00000417
@@ -2897,6 +3067,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);
   @endcode
+  @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PKG_PERF_STATUS         0x00000613
 
@@ -2916,6 +3087,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
 **/
 #define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT        0x00000618
 
@@ -2933,6 +3105,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);
   @endcode
+  @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS      0x00000619
 
@@ -2951,6 +3124,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);
   @endcode
+  @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
 **/
 #define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS        0x0000061B
 
@@ -2969,6 +3143,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
 **/
 #define MSR_SANDY_BRIDGE_DRAM_POWER_INFO         0x0000061C
 
@@ -2987,6 +3162,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL   0x00000C08
 
@@ -3005,6 +3181,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
 **/
 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR   0x00000C09
 
@@ -3023,6 +3200,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0         0x00000C10
 
@@ -3041,6 +3219,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1         0x00000C11
 
@@ -3059,6 +3238,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_U_PMON_CTR0             0x00000C16
 
@@ -3077,6 +3257,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_U_PMON_CTR1             0x00000C17
 
@@ -3095,6 +3276,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL        0x00000C24
 
@@ -3113,6 +3295,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0       0x00000C30
 
@@ -3131,6 +3314,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1       0x00000C31
 
@@ -3149,6 +3333,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2       0x00000C32
 
@@ -3167,6 +3352,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3       0x00000C33
 
@@ -3185,6 +3371,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER     0x00000C34
 
@@ -3203,6 +3390,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR0           0x00000C36
 
@@ -3221,6 +3409,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR1           0x00000C37
 
@@ -3239,6 +3428,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR2           0x00000C38
 
@@ -3257,6 +3447,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR3           0x00000C39
 
@@ -3275,6 +3466,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL         0x00000D04
 
@@ -3293,6 +3485,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0        0x00000D10
 
@@ -3311,6 +3504,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1        0x00000D11
 
@@ -3329,6 +3523,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2        0x00000D12
 
@@ -3347,6 +3542,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3        0x00000D13
 
@@ -3365,6 +3561,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER      0x00000D14
 
@@ -3383,6 +3580,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C0_PMON_CTR0            0x00000D16
 
@@ -3401,6 +3599,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C0_PMON_CTR1            0x00000D17
 
@@ -3419,6 +3618,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C0_PMON_CTR2            0x00000D18
 
@@ -3437,6 +3637,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C0_PMON_CTR3            0x00000D19
 
@@ -3455,6 +3656,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL         0x00000D24
 
@@ -3473,6 +3675,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0        0x00000D30
 
@@ -3491,6 +3694,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1        0x00000D31
 
@@ -3509,6 +3713,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2        0x00000D32
 
@@ -3527,6 +3732,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3        0x00000D33
 
@@ -3545,6 +3751,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER      0x00000D34
 
@@ -3563,6 +3770,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C1_PMON_CTR0            0x00000D36
 
@@ -3581,6 +3789,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C1_PMON_CTR1            0x00000D37
 
@@ -3599,6 +3808,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C1_PMON_CTR2            0x00000D38
 
@@ -3617,6 +3827,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C1_PMON_CTR3            0x00000D39
 
@@ -3635,6 +3846,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL         0x00000D44
 
@@ -3653,6 +3865,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0        0x00000D50
 
@@ -3671,6 +3884,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1        0x00000D51
 
@@ -3689,6 +3903,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2        0x00000D52
 
@@ -3707,6 +3922,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3        0x00000D53
 
@@ -3725,6 +3941,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER      0x00000D54
 
@@ -3743,6 +3960,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C2_PMON_CTR0            0x00000D56
 
@@ -3761,6 +3979,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C2_PMON_CTR1            0x00000D57
 
@@ -3779,6 +3998,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C2_PMON_CTR2            0x00000D58
 
@@ -3797,6 +4017,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C2_PMON_CTR3            0x00000D59
 
@@ -3815,6 +4036,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL         0x00000D64
 
@@ -3833,6 +4055,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0        0x00000D70
 
@@ -3851,6 +4074,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1        0x00000D71
 
@@ -3869,6 +4093,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2        0x00000D72
 
@@ -3887,6 +4112,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3        0x00000D73
 
@@ -3905,6 +4131,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER      0x00000D74
 
@@ -3923,6 +4150,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C3_PMON_CTR0            0x00000D76
 
@@ -3941,6 +4169,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C3_PMON_CTR1            0x00000D77
 
@@ -3959,6 +4188,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C3_PMON_CTR2            0x00000D78
 
@@ -3977,6 +4207,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C3_PMON_CTR3            0x00000D79
 
@@ -3995,6 +4226,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL         0x00000D84
 
@@ -4013,6 +4245,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0        0x00000D90
 
@@ -4031,6 +4264,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1        0x00000D91
 
@@ -4049,6 +4283,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2        0x00000D92
 
@@ -4067,6 +4302,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3        0x00000D93
 
@@ -4085,6 +4321,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER      0x00000D94
 
@@ -4103,6 +4340,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C4_PMON_CTR0            0x00000D96
 
@@ -4121,6 +4359,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C4_PMON_CTR1            0x00000D97
 
@@ -4139,6 +4378,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C4_PMON_CTR2            0x00000D98
 
@@ -4157,6 +4397,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C4_PMON_CTR3            0x00000D99
 
@@ -4175,6 +4416,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL         0x00000DA4
 
@@ -4193,6 +4435,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0        0x00000DB0
 
@@ -4211,6 +4454,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1        0x00000DB1
 
@@ -4229,6 +4473,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2        0x00000DB2
 
@@ -4247,6 +4492,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3        0x00000DB3
 
@@ -4265,6 +4511,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER      0x00000DB4
 
@@ -4283,6 +4530,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C5_PMON_CTR0            0x00000DB6
 
@@ -4301,6 +4549,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C5_PMON_CTR1            0x00000DB7
 
@@ -4319,6 +4568,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C5_PMON_CTR2            0x00000DB8
 
@@ -4337,6 +4587,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C5_PMON_CTR3            0x00000DB9
 
@@ -4355,6 +4606,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL         0x00000DC4
 
@@ -4373,6 +4625,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0        0x00000DD0
 
@@ -4391,6 +4644,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1        0x00000DD1
 
@@ -4409,6 +4663,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2        0x00000DD2
 
@@ -4427,6 +4682,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3        0x00000DD3
 
@@ -4445,6 +4701,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER      0x00000DD4
 
@@ -4463,6 +4720,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C6_PMON_CTR0            0x00000DD6
 
@@ -4481,6 +4739,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C6_PMON_CTR1            0x00000DD7
 
@@ -4499,6 +4758,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C6_PMON_CTR2            0x00000DD8
 
@@ -4517,6 +4777,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C6_PMON_CTR3            0x00000DD9
 
@@ -4535,6 +4796,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL         0x00000DE4
 
@@ -4553,6 +4815,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0        0x00000DF0
 
@@ -4571,6 +4834,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1        0x00000DF1
 
@@ -4589,6 +4853,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2        0x00000DF2
 
@@ -4607,6 +4872,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3        0x00000DF3
 
@@ -4625,6 +4891,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER      0x00000DF4
 
@@ -4643,6 +4910,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C7_PMON_CTR0            0x00000DF6
 
@@ -4661,6 +4929,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C7_PMON_CTR1            0x00000DF7
 
@@ -4679,6 +4948,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C7_PMON_CTR2            0x00000DF8
 
@@ -4697,6 +4967,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);
   AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);
   @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
 **/
 #define MSR_SANDY_BRIDGE_C7_PMON_CTR3            0x00000DF9
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 15/20] UefiCpuPkg/SilvermontMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (13 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 14/20] UefiCpuPkg/SandyBridgeMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 16/20] UefiCpuPkg/SkylakeMsr.h: " Jeff Fan
                   ` (4 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 57 +++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
index 4272375..335ebb2 100644
--- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
   @endcode
+  @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
 **/
 #define MSR_SILVERMONT_PLATFORM_ID               0x00000017
 
@@ -89,6 +90,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_SILVERMONT_EBL_CR_POWERON            0x0000002A
 
@@ -190,6 +192,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);
   @endcode
+  @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 **/
 #define MSR_SILVERMONT_SMI_COUNT                 0x00000034
 
@@ -238,6 +241,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
   @endcode
+  @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
   @{
 **/
 #define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP      0x00000040
@@ -268,6 +279,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
   @endcode
+  @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
   @{
 **/
 #define MSR_SILVERMONT_LASTBRANCH_0_TO_IP        0x00000060
@@ -297,6 +316,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
   @endcode
+  @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 **/
 #define MSR_SILVERMONT_FSB_FREQ                  0x000000CD
 
@@ -364,6 +384,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL    0x000000E2
 
@@ -428,6 +449,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);
   AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
 **/
 #define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE       0x000000E4
 
@@ -486,6 +508,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_SILVERMONT_BBL_CR_CTL3               0x0000011E
 
@@ -545,6 +568,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);
   AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
 **/
 #define MSR_SILVERMONT_FEATURE_CONFIG            0x0000013C
 
@@ -597,6 +621,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_SILVERMONT_IA32_MISC_ENABLE          0x000001A0
 
@@ -697,6 +722,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
 **/
 #define MSR_SILVERMONT_TEMPERATURE_TARGET        0x000001A2
 
@@ -750,6 +776,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);
   AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);
   @endcode
+  @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
 **/
 #define MSR_SILVERMONT_OFFCORE_RSP_0             0x000001A6
 
@@ -768,6 +795,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);
   AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);
   @endcode
+  @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 **/
 #define MSR_SILVERMONT_OFFCORE_RSP_1             0x000001A7
 
@@ -788,6 +816,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);
   AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_SILVERMONT_TURBO_RATIO_LIMIT         0x000001AD
 
@@ -863,6 +892,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_SILVERMONT_LASTBRANCH_TOS            0x000001C9
 
@@ -882,6 +912,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);
   @endcode
+  @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_SILVERMONT_LER_FROM_LIP              0x000001DD
 
@@ -902,6 +933,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);
   @endcode
+  @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_SILVERMONT_LER_TO_LIP                0x000001DE
 
@@ -921,6 +953,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS, Msr);
   @endcode
+  @note MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS    0x0000038E
 
@@ -942,6 +975,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);
   AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
 **/
 #define MSR_SILVERMONT_PEBS_ENABLE               0x000003F1
 
@@ -988,6 +1022,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);
   AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);
   @endcode
+  @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
 **/
 #define MSR_SILVERMONT_PKG_C6_RESIDENCY          0x000003FA
 
@@ -1009,6 +1044,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);
   AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);
   @endcode
+  @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
 **/
 #define MSR_SILVERMONT_CORE_C6_RESIDENCY         0x000003FD
 
@@ -1027,6 +1063,9 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_CTL);
   AsmWriteMsr64 (MSR_SILVERMONT_MC3_CTL, Msr);
   @endcode
+  @note MSR_SILVERMONT_MC3_CTL is defined as MSR_MC3_CTL in SDM.
+        MSR_SILVERMONT_MC4_CTL is defined as MSR_MC4_CTL in SDM.
+        MSR_SILVERMONT_MC5_CTL is defined as MSR_MC5_CTL in SDM.
   @{
 **/
 #define MSR_SILVERMONT_MC3_CTL                   0x0000040C
@@ -1049,6 +1088,9 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_STATUS);
   AsmWriteMsr64 (MSR_SILVERMONT_MC3_STATUS, Msr);
   @endcode
+  @note MSR_SILVERMONT_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
+        MSR_SILVERMONT_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
+        MSR_SILVERMONT_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
   @{
 **/
 #define MSR_SILVERMONT_MC3_STATUS                0x0000040D
@@ -1074,6 +1116,9 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_ADDR);
   AsmWriteMsr64 (MSR_SILVERMONT_MC3_ADDR, Msr);
   @endcode
+  @note MSR_SILVERMONT_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
+        MSR_SILVERMONT_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
+        MSR_SILVERMONT_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
   @{
 **/
 #define MSR_SILVERMONT_MC3_ADDR                  0x0000040E
@@ -1095,6 +1140,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);
   @endcode
+  @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
 **/
 #define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM    0x0000048C
 
@@ -1113,6 +1159,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);
   @endcode
+  @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
 **/
 #define MSR_SILVERMONT_IA32_VMX_FMFUNC           0x00000491
 
@@ -1134,6 +1181,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);
   AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);
   @endcode
+  @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.
 **/
 #define MSR_SILVERMONT_CORE_C1_RESIDENCY         0x00000660
 
@@ -1154,6 +1202,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);
   @endcode
+  @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
 **/
 #define MSR_SILVERMONT_RAPL_POWER_UNIT           0x00000606
 
@@ -1216,6 +1265,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);
   AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
 **/
 #define MSR_SILVERMONT_PKG_POWER_LIMIT           0x00000610
 
@@ -1275,6 +1325,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);
   @endcode
+  @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
 **/
 #define MSR_SILVERMONT_PKG_ENERGY_STATUS         0x00000611
 
@@ -1293,6 +1344,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);
   @endcode
+  @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
 **/
 #define MSR_SILVERMONT_PP0_ENERGY_STATUS         0x00000639
 
@@ -1312,6 +1364,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);
   AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);
   @endcode
+  @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.
 **/
 #define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668
 
@@ -1332,6 +1385,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);
   AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);
   @endcode
+  @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.
 **/
 #define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669
 
@@ -1352,6 +1406,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);
   @endcode
+  @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.
 **/
 #define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER     0x00000664
 
@@ -1371,6 +1426,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);
   @endcode
+  @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
 **/
 #define MSR_SILVERMONT_PKG_POWER_INFO            0x0000066E
 
@@ -1419,6 +1475,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);
   AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);
   @endcode
+  @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
 **/
 #define MSR_SILVERMONT_PP0_POWER_LIMIT           0x00000638
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 16/20] UefiCpuPkg/SkylakeMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (14 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 15/20] UefiCpuPkg/SilvermontMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 17/20] UefiCpuPkg/Xeon5600Msr.h: " Jeff Fan
                   ` (3 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 83 ++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 34868f9..604b98f 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -42,6 +42,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_SKYLAKE_TURBO_RATIO_LIMIT            0x000001AD
 
@@ -101,6 +102,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_SKYLAKE_LASTBRANCH_TOS               0x000001C9
 
@@ -119,6 +121,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
   @endcode
+  @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
 **/
 #define MSR_SKYLAKE_SGXOWNER0                    0x00000300
 
@@ -137,6 +140,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
   @endcode
+  @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
 **/
 #define MSR_SKYLAKE_SGXOWNER1                    0x00000301
 
@@ -158,6 +162,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS       0x0000038E
 
@@ -269,6 +274,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
   AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
 **/
 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
 
@@ -381,6 +387,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
   AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
 **/
 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET  0x00000391
 
@@ -489,6 +496,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
   AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.
 **/
 #define MSR_SKYLAKE_PEBS_FRONTEND                0x000003F7
 
@@ -549,6 +557,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);
   @endcode
+  @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.
 **/
 #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER      0x0000064D
 
@@ -596,6 +605,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);
   @endcode
+  @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.
 **/
 #define MSR_SKYLAKE_PPERF                        0x0000064E
 
@@ -616,6 +626,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
   AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.
 **/
 #define MSR_SKYLAKE_PKG_HDC_CONFIG               0x00000652
 
@@ -659,6 +670,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);
   @endcode
+  @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.
 **/
 #define MSR_SKYLAKE_CORE_HDC_RESIDENCY           0x00000653
 
@@ -677,6 +689,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);
   @endcode
+  @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.
 **/
 #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY    0x00000655
 
@@ -694,6 +707,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);
   @endcode
+  @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.
 **/
 #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY       0x00000656
 
@@ -714,6 +728,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);
   @endcode
+  @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.
 **/
 #define MSR_SKYLAKE_WEIGHTED_CORE_C0             0x00000658
 
@@ -733,6 +748,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);
   @endcode
+  @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.
 **/
 #define MSR_SKYLAKE_ANY_CORE_C0                  0x00000659
 
@@ -752,6 +768,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);
   @endcode
+  @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.
 **/
 #define MSR_SKYLAKE_ANY_GFXE_C0                  0x0000065A
 
@@ -772,6 +789,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);
   @endcode
+  @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.
 **/
 #define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0         0x0000065B
 
@@ -798,6 +816,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);
   AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);
   @endcode
+  @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.
 **/
 #define MSR_SKYLAKE_PLATFORM_POWER_LIMIT         0x0000065C
 
@@ -893,6 +912,22 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);
   AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);
   @endcode
+  @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
   @{
 **/
 #define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP        0x00000690
@@ -930,6 +965,22 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);
   AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);
   @endcode
+  @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
   @{
 **/
 #define MSR_SKYLAKE_LASTBRANCH_16_TO_IP          0x000006D0
@@ -969,6 +1020,38 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);
   AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);
   @endcode
+  @note MSR_SKYLAKE_LBR_INFO_0  is defined as MSR_LBR_INFO_0  in SDM.
+        MSR_SKYLAKE_LBR_INFO_1  is defined as MSR_LBR_INFO_1  in SDM.
+        MSR_SKYLAKE_LBR_INFO_2  is defined as MSR_LBR_INFO_2  in SDM.
+        MSR_SKYLAKE_LBR_INFO_3  is defined as MSR_LBR_INFO_3  in SDM.
+        MSR_SKYLAKE_LBR_INFO_4  is defined as MSR_LBR_INFO_4  in SDM.
+        MSR_SKYLAKE_LBR_INFO_5  is defined as MSR_LBR_INFO_5  in SDM.
+        MSR_SKYLAKE_LBR_INFO_6  is defined as MSR_LBR_INFO_6  in SDM.
+        MSR_SKYLAKE_LBR_INFO_7  is defined as MSR_LBR_INFO_7  in SDM.
+        MSR_SKYLAKE_LBR_INFO_8  is defined as MSR_LBR_INFO_8  in SDM.
+        MSR_SKYLAKE_LBR_INFO_9  is defined as MSR_LBR_INFO_9  in SDM.
+        MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.
+        MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.
+        MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.
+        MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.
+        MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.
+        MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.
+        MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.
+        MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.
+        MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.
+        MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.
+        MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.
+        MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.
+        MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.
+        MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.
+        MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.
+        MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.
+        MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.
+        MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.
+        MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.
+        MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.
+        MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.
+        MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.
   @{
 **/
 #define MSR_SKYLAKE_LBR_INFO_0                   0x00000DC0
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 17/20] UefiCpuPkg/Xeon5600Msr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (15 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 16/20] UefiCpuPkg/SkylakeMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 18/20] UefiCpuPkg/XeonDMsr.h: " Jeff Fan
                   ` (2 subsequent siblings)
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
index a4c6ba0..504c76b 100644
--- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
@@ -43,6 +43,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
   AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
 **/
 #define MSR_XEON_5600_FEATURE_CONFIG             0x0000013C
 
@@ -92,6 +93,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
   AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
   @endcode
+  @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 **/
 #define MSR_XEON_5600_OFFCORE_RSP_1              0x000001A7
 
@@ -112,6 +114,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_XEON_5600_TURBO_RATIO_LIMIT          0x000001AD
 
@@ -176,6 +179,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
   AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
   @endcode
+  @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
 **/
 #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS      0x000001B0
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 18/20] UefiCpuPkg/XeonDMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (16 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 17/20] UefiCpuPkg/Xeon5600Msr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 19/20] UefiCpuPkg/XeonE7Msr.h: " Jeff Fan
  2016-09-06 11:38 ` [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: " Jeff Fan
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 106 +++++++++++++++++++++++++++++
 1 file changed, 106 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
index 43a35f2..0a88eb0 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -42,6 +42,7 @@
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);
   AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
 **/
 #define MSR_XEON_D_PPIN_CTL                      0x0000004E
 
@@ -89,6 +90,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);
   @endcode
+  @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.
 **/
 #define MSR_XEON_D_PPIN                          0x0000004F
 
@@ -109,6 +111,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_XEON_D_PLATFORM_INFO                 0x000000CE
 
@@ -178,6 +181,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_XEON_D_PKG_CST_CONFIG_CONTROL        0x000000E2
 
@@ -268,6 +272,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);
   @endcode
+  @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
 **/
 #define MSR_XEON_D_IA32_MCG_CAP                  0x00000179
 
@@ -347,6 +352,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);
   AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
 **/
 #define MSR_XEON_D_SMM_MCA_CAP                   0x0000017D
 
@@ -397,6 +403,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
 **/
 #define MSR_XEON_D_TEMPERATURE_TARGET            0x000001A2
 
@@ -447,6 +454,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);
   @endcode
+  @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_XEON_D_TURBO_RATIO_LIMIT             0x000001AD
 
@@ -514,6 +522,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);
   @endcode
+  @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
 **/
 #define MSR_XEON_D_TURBO_RATIO_LIMIT1            0x000001AE
 
@@ -580,6 +589,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);
   @endcode
+  @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
 **/
 #define MSR_XEON_D_RAPL_POWER_UNIT               0x00000606
 
@@ -638,6 +648,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);
   AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
 **/
 #define MSR_XEON_D_DRAM_POWER_LIMIT              0x00000618
 
@@ -655,6 +666,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);
   @endcode
+  @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
 **/
 #define MSR_XEON_D_DRAM_ENERGY_STATUS            0x00000619
 
@@ -673,6 +685,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);
   @endcode
+  @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
 **/
 #define MSR_XEON_D_DRAM_PERF_STATUS              0x0000061B
 
@@ -691,6 +704,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);
   AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);
   @endcode
+  @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
 **/
 #define MSR_XEON_D_DRAM_POWER_INFO               0x0000061C
 
@@ -712,6 +726,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);
   AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
 **/
 #define MSR_XEON_D_CORE_PERF_LIMIT_REASONS       0x00000690
 
@@ -891,6 +906,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);
   AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
 **/
 #define MSR_XEON_D_IA32_QM_EVTSEL                0x00000C8D
 
@@ -938,6 +954,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);
   AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
 **/
 #define MSR_XEON_D_IA32_PQR_ASSOC                0x00000C8F
 
@@ -984,6 +1001,22 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
   AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_IA32_L3_QOS_MASK_0  is defined as IA32_L3_QOS_MASK_0  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_1  is defined as IA32_L3_QOS_MASK_1  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_2  is defined as IA32_L3_QOS_MASK_2  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_3  is defined as IA32_L3_QOS_MASK_3  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_4  is defined as IA32_L3_QOS_MASK_4  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_5  is defined as IA32_L3_QOS_MASK_5  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_6  is defined as IA32_L3_QOS_MASK_6  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_7  is defined as IA32_L3_QOS_MASK_7  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_8  is defined as IA32_L3_QOS_MASK_8  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_9  is defined as IA32_L3_QOS_MASK_9  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
   @{
 **/
 #define MSR_XEON_D_IA32_L3_QOS_MASK_0            0x00000C90
@@ -1047,6 +1080,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);
   @endcode
+  @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.
 **/
 #define MSR_XEON_D_TURBO_RATIO_LIMIT3            0x000001AC
 
@@ -1105,6 +1139,23 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_D_MC5_CTL);
   AsmWriteMsr64 (MSR_XEON_D_MC5_CTL, Msr);
   @endcode
+  @note MSR_XEON_D_MC5_CTL  is defined as MSR_MC5_CTL  in SDM.
+        MSR_XEON_D_MC6_CTL  is defined as MSR_MC6_CTL  in SDM.
+        MSR_XEON_D_MC7_CTL  is defined as MSR_MC7_CTL  in SDM.
+        MSR_XEON_D_MC8_CTL  is defined as MSR_MC8_CTL  in SDM.
+        MSR_XEON_D_MC9_CTL  is defined as MSR_MC9_CTL  in SDM.
+        MSR_XEON_D_MC10_CTL is defined as MSR_MC10_CTL in SDM.
+        MSR_XEON_D_MC11_CTL is defined as MSR_MC11_CTL in SDM.
+        MSR_XEON_D_MC12_CTL is defined as MSR_MC12_CTL in SDM.
+        MSR_XEON_D_MC13_CTL is defined as MSR_MC13_CTL in SDM.
+        MSR_XEON_D_MC14_CTL is defined as MSR_MC14_CTL in SDM.
+        MSR_XEON_D_MC15_CTL is defined as MSR_MC15_CTL in SDM.
+        MSR_XEON_D_MC16_CTL is defined as MSR_MC16_CTL in SDM.
+        MSR_XEON_D_MC17_CTL is defined as MSR_MC17_CTL in SDM.
+        MSR_XEON_D_MC18_CTL is defined as MSR_MC18_CTL in SDM.
+        MSR_XEON_D_MC19_CTL is defined as MSR_MC19_CTL in SDM.
+        MSR_XEON_D_MC20_CTL is defined as MSR_MC20_CTL in SDM.
+        MSR_XEON_D_MC21_CTL is defined as MSR_MC21_CTL in SDM.
   @{
 **/
 #define MSR_XEON_D_MC5_CTL                       0x00000414
@@ -1141,6 +1192,23 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_D_MC6_STATUS);
   AsmWriteMsr64 (MSR_XEON_D_MC6_STATUS, Msr);
   @endcode
+  @note MSR_XEON_D_MC5_STATUS  is defined as MSR_MC5_STATUS  in SDM.
+        MSR_XEON_D_MC6_STATUS  is defined as MSR_MC6_STATUS  in SDM.
+        MSR_XEON_D_MC7_STATUS  is defined as MSR_MC7_STATUS  in SDM.
+        MSR_XEON_D_MC8_STATUS  is defined as MSR_MC8_STATUS  in SDM.
+        MSR_XEON_D_MC9_STATUS  is defined as MSR_MC9_STATUS  in SDM.
+        MSR_XEON_D_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
+        MSR_XEON_D_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
+        MSR_XEON_D_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
+        MSR_XEON_D_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
+        MSR_XEON_D_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
+        MSR_XEON_D_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
+        MSR_XEON_D_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
+        MSR_XEON_D_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
+        MSR_XEON_D_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
+        MSR_XEON_D_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
+        MSR_XEON_D_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.
+        MSR_XEON_D_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.
   @{
 **/
 #define MSR_XEON_D_MC5_STATUS                    0x00000415
@@ -1177,6 +1245,23 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_D_MC6_ADDR);
   AsmWriteMsr64 (MSR_XEON_D_MC6_ADDR, Msr);
   @endcode
+  @note MSR_XEON_D_MC5_ADDR  is defined as MSR_MC5_ADDR  in SDM.
+        MSR_XEON_D_MC6_ADDR  is defined as MSR_MC6_ADDR  in SDM.
+        MSR_XEON_D_MC7_ADDR  is defined as MSR_MC7_ADDR  in SDM.
+        MSR_XEON_D_MC8_ADDR  is defined as MSR_MC8_ADDR  in SDM.
+        MSR_XEON_D_MC9_ADDR  is defined as MSR_MC9_ADDR  in SDM.
+        MSR_XEON_D_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
+        MSR_XEON_D_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
+        MSR_XEON_D_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
+        MSR_XEON_D_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
+        MSR_XEON_D_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
+        MSR_XEON_D_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
+        MSR_XEON_D_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
+        MSR_XEON_D_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
+        MSR_XEON_D_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
+        MSR_XEON_D_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
+        MSR_XEON_D_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.
+        MSR_XEON_D_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.
   @{
 **/
 #define MSR_XEON_D_MC5_ADDR                      0x00000416
@@ -1214,6 +1299,23 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_D_MC6_MISC);
   AsmWriteMsr64 (MSR_XEON_D_MC6_MISC, Msr);
   @endcode
+  @note MSR_XEON_D_MC5_MISC  is defined as MSR_MC5_MISC  in SDM.
+        MSR_XEON_D_MC6_MISC  is defined as MSR_MC6_MISC  in SDM.
+        MSR_XEON_D_MC7_MISC  is defined as MSR_MC7_MISC  in SDM.
+        MSR_XEON_D_MC8_MISC  is defined as MSR_MC8_MISC  in SDM.
+        MSR_XEON_D_MC9_MISC  is defined as MSR_MC9_MISC  in SDM.
+        MSR_XEON_D_MC10_MISC is defined as MSR_MC10_MISC in SDM.
+        MSR_XEON_D_MC11_MISC is defined as MSR_MC11_MISC in SDM.
+        MSR_XEON_D_MC12_MISC is defined as MSR_MC12_MISC in SDM.
+        MSR_XEON_D_MC13_MISC is defined as MSR_MC13_MISC in SDM.
+        MSR_XEON_D_MC14_MISC is defined as MSR_MC14_MISC in SDM.
+        MSR_XEON_D_MC15_MISC is defined as MSR_MC15_MISC in SDM.
+        MSR_XEON_D_MC16_MISC is defined as MSR_MC16_MISC in SDM.
+        MSR_XEON_D_MC17_MISC is defined as MSR_MC17_MISC in SDM.
+        MSR_XEON_D_MC18_MISC is defined as MSR_MC18_MISC in SDM.
+        MSR_XEON_D_MC19_MISC is defined as MSR_MC19_MISC in SDM.
+        MSR_XEON_D_MC20_MISC is defined as MSR_MC20_MISC in SDM.
+        MSR_XEON_D_MC21_MISC is defined as MSR_MC21_MISC in SDM.
   @{
 **/
 #define MSR_XEON_D_MC5_MISC                      0x00000417
@@ -1253,6 +1355,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY);
   AsmWriteMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.
 **/
 #define MSR_XEON_D_PKG_C8_RESIDENCY              0x00000630
 
@@ -1302,6 +1405,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY);
   AsmWriteMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.
 **/
 #define MSR_XEON_D_PKG_C9_RESIDENCY              0x00000631
 
@@ -1351,6 +1455,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY);
   AsmWriteMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
 **/
 #define MSR_XEON_D_PKG_C10_RESIDENCY             0x00000632
 
@@ -1399,6 +1504,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);
   AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);
   @endcode
+  @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
 **/
 #define MSR_XEON_D_IA32_L3_QOS_CFG               0x00000C81
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 19/20] UefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (17 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 18/20] UefiCpuPkg/XeonDMsr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 11:38 ` [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: " Jeff Fan
  19 siblings, 0 replies; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 31 +++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
index b95f963..3128c4b 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
   AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
   @endcode
+  @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD
 
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40
 
@@ -76,6 +78,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41
 
@@ -94,6 +97,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42
 
@@ -112,6 +116,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
   @{
 **/
 #define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50
@@ -137,6 +147,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
   @endcode
+  @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
   @{
 **/
 #define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51
@@ -162,6 +178,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
   @endcode
+  @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
 **/
 #define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0
 
@@ -180,6 +197,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
   @endcode
+  @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
 **/
 #define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1
 
@@ -198,6 +216,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
   @endcode
+  @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
 **/
 #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2
 
@@ -216,6 +235,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
   @endcode
+  @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
   @{
 **/
 #define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0
@@ -241,6 +266,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
   @endcode
+  @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
   @{
 **/
 #define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
                   ` (18 preceding siblings ...)
  2016-09-06 11:38 ` [Patch 19/20] UefiCpuPkg/XeonE7Msr.h: " Jeff Fan
@ 2016-09-06 11:38 ` Jeff Fan
  2016-09-06 17:27   ` Mudusuru, Giri P
  19 siblings, 1 reply; 22+ messages in thread
From: Jeff Fan @ 2016-09-06 11:38 UTC (permalink / raw)
  To: edk2-devel; +Cc: Michael Kinney, Feng Tian, Giri P Mudusuru

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 51 ++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index 6695b69..75f2dce 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
   @endcode
+  @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 **/
 #define MSR_XEON_PHI_SMI_COUNT                   0x00000034
 
@@ -85,6 +86,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
   AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
 **/
 #define MSR_XEON_PHI_PLATFORM_INFO               0x000000CE
 
@@ -151,6 +153,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
   AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 **/
 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL      0x000000E2
 
@@ -208,6 +211,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
   AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
 **/
 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE         0x000000E4
 
@@ -261,6 +265,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
   AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
 **/
 #define MSR_XEON_PHI_FEATURE_CONFIG              0x0000013C
 
@@ -313,6 +318,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_XEON_PHI_IA32_MISC_ENABLE            0x000001A0
 
@@ -402,6 +408,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
   AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
 **/
 #define MSR_XEON_PHI_TEMPERATURE_TARGET          0x000001A2
 
@@ -450,6 +457,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
   AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
   @endcode
+  @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
 **/
 #define MSR_XEON_PHI_OFFCORE_RSP_0               0x000001A6
 
@@ -468,6 +476,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
   AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
   @endcode
+  @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 **/
 #define MSR_XEON_PHI_OFFCORE_RSP_1               0x000001A7
 
@@ -488,6 +497,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
   AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 **/
 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT           0x000001AD
 
@@ -612,6 +622,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
   AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
   @endcode
+  @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
 **/
 #define MSR_XEON_PHI_LBR_SELECT                  0x000001C8
 
@@ -630,6 +641,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_XEON_PHI_LASTBRANCH_TOS              0x000001C9
 
@@ -647,6 +659,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
   @endcode
+  @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_XEON_PHI_LER_FROM_LIP                0x000001DD
 
@@ -664,6 +677,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
   @endcode
+  @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_XEON_PHI_LER_TO_LIP                  0x000001DE
 
@@ -682,6 +696,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);
   @endcode
+  @note MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS      0x0000038E
 
@@ -700,6 +715,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
   AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
   @endcode
+  @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
 **/
 #define MSR_XEON_PHI_PEBS_ENABLE                 0x000003F1
 
@@ -720,6 +736,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
   AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
   @endcode
+  @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
 **/
 #define MSR_XEON_PHI_PKG_C3_RESIDENCY            0x000003F8
 
@@ -738,6 +755,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
   AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
   @endcode
+  @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
 **/
 #define MSR_XEON_PHI_PKG_C6_RESIDENCY            0x000003F9
 
@@ -756,6 +774,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
   AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
   @endcode
+  @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
 **/
 #define MSR_XEON_PHI_PKG_C7_RESIDENCY            0x000003FA
 
@@ -776,6 +795,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
   AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
 **/
 #define MSR_XEON_PHI_MC0_RESIDENCY               0x000003FC
 
@@ -794,6 +814,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
   AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
 **/
 #define MSR_XEON_PHI_MC6_RESIDENCY               0x000003FD
 
@@ -814,6 +835,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
   AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
   @endcode
+  @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
 **/
 #define MSR_XEON_PHI_CORE_C6_RESIDENCY           0x000003FF
 
@@ -832,6 +854,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL);
   AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC3_CTL is defined as MSR_MC3_CTL in SDM.
 **/
 #define MSR_XEON_PHI_MC3_CTL                     0x0000040C
 
@@ -850,6 +873,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS);
   AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
 **/
 #define MSR_XEON_PHI_MC3_STATUS                  0x0000040D
 
@@ -868,6 +892,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR);
   AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
 **/
 #define MSR_XEON_PHI_MC3_ADDR                    0x0000040E
 
@@ -886,6 +911,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL);
   AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC4_CTL is defined as MSR_MC4_CTL in SDM.
 **/
 #define MSR_XEON_PHI_MC4_CTL                     0x00000410
 
@@ -904,6 +930,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS);
   AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
 **/
 #define MSR_XEON_PHI_MC4_STATUS                  0x00000411
 
@@ -925,6 +952,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR);
   AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
 **/
 #define MSR_XEON_PHI_MC4_ADDR                    0x00000412
 
@@ -943,6 +971,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL);
   AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC5_CTL is defined as MSR_MC5_CTL in SDM.
 **/
 #define MSR_XEON_PHI_MC5_CTL                     0x00000414
 
@@ -961,6 +990,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS);
   AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
 **/
 #define MSR_XEON_PHI_MC5_STATUS                  0x00000415
 
@@ -979,6 +1009,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR);
   AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr);
   @endcode
+  @note MSR_XEON_PHI_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
 **/
 #define MSR_XEON_PHI_MC5_ADDR                    0x00000416
 
@@ -996,6 +1027,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
   @endcode
+  @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
 **/
 #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM      0x0000048C
 
@@ -1014,6 +1046,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
   @endcode
+  @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
 **/
 #define MSR_XEON_PHI_IA32_VMX_FMFUNC             0x00000491
 
@@ -1033,6 +1066,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
   @endcode
+  @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
 **/
 #define MSR_XEON_PHI_RAPL_POWER_UNIT             0x00000606
 
@@ -1092,6 +1126,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
   AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
   @endcode
+  @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
 **/
 #define MSR_XEON_PHI_PKG_C2_RESIDENCY            0x0000060D
 
@@ -1111,6 +1146,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
   AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
 **/
 #define MSR_XEON_PHI_PKG_POWER_LIMIT             0x00000610
 
@@ -1128,6 +1164,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
   @endcode
+  @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
 **/
 #define MSR_XEON_PHI_PKG_ENERGY_STATUS           0x00000611
 
@@ -1145,6 +1182,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
   @endcode
+  @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
 **/
 #define MSR_XEON_PHI_PKG_PERF_STATUS             0x00000613
 
@@ -1164,6 +1202,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
   AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
   @endcode
+  @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
 **/
 #define MSR_XEON_PHI_PKG_POWER_INFO              0x00000614
 
@@ -1183,6 +1222,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
   AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
 **/
 #define MSR_XEON_PHI_DRAM_POWER_LIMIT            0x00000618
 
@@ -1200,6 +1240,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
   @endcode
+  @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
 **/
 #define MSR_XEON_PHI_DRAM_ENERGY_STATUS          0x00000619
 
@@ -1218,6 +1259,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
   @endcode
+  @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
 **/
 #define MSR_XEON_PHI_DRAM_PERF_STATUS            0x0000061B
 
@@ -1236,6 +1278,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
   AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
   @endcode
+  @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
 **/
 #define MSR_XEON_PHI_DRAM_POWER_INFO             0x0000061C
 
@@ -1255,6 +1298,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
   AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
   @endcode
+  @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
 **/
 #define MSR_XEON_PHI_PP0_POWER_LIMIT             0x00000638
 
@@ -1273,6 +1317,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
   @endcode
+  @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
 **/
 #define MSR_XEON_PHI_PP0_ENERGY_STATUS           0x00000639
 
@@ -1290,6 +1335,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
   @endcode
+  @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
 **/
 #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL          0x00000648
 
@@ -1307,6 +1353,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
   @endcode
+  @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
 **/
 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1           0x00000649
 
@@ -1324,6 +1371,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
   @endcode
+  @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
 **/
 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2           0x0000064A
 
@@ -1342,6 +1390,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
   AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
   @endcode
+  @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
 **/
 #define MSR_XEON_PHI_CONFIG_TDP_CONTROL          0x0000064B
 
@@ -1360,6 +1409,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
   AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
   @endcode
+  @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
 **/
 #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO      0x0000064C
 
@@ -1381,6 +1431,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
   AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
   @endcode
+  @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
 **/
 #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS     0x00000690
 
-- 
2.9.3.windows.2



^ permalink raw reply related	[flat|nested] 22+ messages in thread

* Re: [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment
  2016-09-06 11:38 ` [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: " Jeff Fan
@ 2016-09-06 17:27   ` Mudusuru, Giri P
  0 siblings, 0 replies; 22+ messages in thread
From: Mudusuru, Giri P @ 2016-09-06 17:27 UTC (permalink / raw)
  To: Fan, Jeff, edk2-devel@lists.01.org; +Cc: Kinney, Michael D, Tian, Feng

Thanks Jeff for adding comments to refer the SDM naming.

Reviewed series of patches.

Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> 

> -----Original Message-----
> From: Fan, Jeff
> Sent: Tuesday, September 6, 2016 4:39 AM
> To: edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Tian, Feng
> <feng.tian@intel.com>; Mudusuru, Giri P <giri.p.mudusuru@intel.com>
> Subject: [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM
> in comment
> 
> Cc: Michael Kinney <michael.d.kinney@intel.com>
> Cc: Feng Tian <feng.tian@intel.com>
> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jeff Fan <jeff.fan@intel.com>
> ---
>  UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 51
> ++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> index 6695b69..75f2dce 100644
> --- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> +++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
> @@ -41,6 +41,7 @@
> 
>    Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
>    @endcode
> +  @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
>  **/
>  #define MSR_XEON_PHI_SMI_COUNT                   0x00000034
> 
> @@ -85,6 +86,7 @@ typedef union {
>    Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
>    AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
>    @endcode
> +  @note MSR_XEON_PHI_PLATFORM_INFO is defined as
> MSR_PLATFORM_INFO in SDM.
>  **/
>  #define MSR_XEON_PHI_PLATFORM_INFO               0x000000CE
> 
> @@ -151,6 +153,7 @@ typedef union {
>    Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
>    AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
>    @endcode
> +  @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as
> MSR_PKG_CST_CONFIG_CONTROL in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL      0x000000E2
> 
> @@ -208,6 +211,7 @@ typedef union {
>    Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
>    AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
>    @endcode
> +  @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as
> MSR_PMG_IO_CAPTURE_BASE in SDM.
>  **/
>  #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE         0x000000E4
> 
> @@ -261,6 +265,7 @@ typedef union {
>    Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
>    AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
>    @endcode
> +  @note MSR_XEON_PHI_FEATURE_CONFIG is defined as
> MSR_FEATURE_CONFIG in SDM.
>  **/
>  #define MSR_XEON_PHI_FEATURE_CONFIG              0x0000013C
> 
> @@ -313,6 +318,7 @@ typedef union {
>    Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
>    AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
>    @endcode
> +  @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as
> IA32_MISC_ENABLE in SDM.
>  **/
>  #define MSR_XEON_PHI_IA32_MISC_ENABLE            0x000001A0
> 
> @@ -402,6 +408,7 @@ typedef union {
>    Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
>    AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
>    @endcode
> +  @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as
> MSR_TEMPERATURE_TARGET in SDM.
>  **/
>  #define MSR_XEON_PHI_TEMPERATURE_TARGET          0x000001A2
> 
> @@ -450,6 +457,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
>    AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0
> in SDM.
>  **/
>  #define MSR_XEON_PHI_OFFCORE_RSP_0               0x000001A6
> 
> @@ -468,6 +476,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
>    AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1
> in SDM.
>  **/
>  #define MSR_XEON_PHI_OFFCORE_RSP_1               0x000001A7
> 
> @@ -488,6 +497,7 @@ typedef union {
>    Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
>    AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
>    @endcode
> +  @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as
> MSR_TURBO_RATIO_LIMIT in SDM.
>  **/
>  #define MSR_XEON_PHI_TURBO_RATIO_LIMIT           0x000001AD
> 
> @@ -612,6 +622,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
>    AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
>  **/
>  #define MSR_XEON_PHI_LBR_SELECT                  0x000001C8
> 
> @@ -630,6 +641,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
>    AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as
> MSR_LASTBRANCH_TOS in SDM.
>  **/
>  #define MSR_XEON_PHI_LASTBRANCH_TOS              0x000001C9
> 
> @@ -647,6 +659,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
>    @endcode
> +  @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in
> SDM.
>  **/
>  #define MSR_XEON_PHI_LER_FROM_LIP                0x000001DD
> 
> @@ -664,6 +677,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
>    @endcode
> +  @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
>  **/
>  #define MSR_XEON_PHI_LER_TO_LIP                  0x000001DE
> 
> @@ -682,6 +696,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);
>    AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS is defined as
> IA32_PERF_GLOBAL_STAUS in SDM.
>  **/
>  #define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS      0x0000038E
> 
> @@ -700,6 +715,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
>    AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in
> SDM.
>  **/
>  #define MSR_XEON_PHI_PEBS_ENABLE                 0x000003F1
> 
> @@ -720,6 +736,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
>    AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as
> MSR_PKG_C3_RESIDENCY in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_C3_RESIDENCY            0x000003F8
> 
> @@ -738,6 +755,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
>    AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as
> MSR_PKG_C6_RESIDENCY in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_C6_RESIDENCY            0x000003F9
> 
> @@ -756,6 +774,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
>    AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as
> MSR_PKG_C7_RESIDENCY in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_C7_RESIDENCY            0x000003FA
> 
> @@ -776,6 +795,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC0_RESIDENCY is defined as
> MSR_MC0_RESIDENCY in SDM.
>  **/
>  #define MSR_XEON_PHI_MC0_RESIDENCY               0x000003FC
> 
> @@ -794,6 +814,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC6_RESIDENCY is defined as
> MSR_MC6_RESIDENCY in SDM.
>  **/
>  #define MSR_XEON_PHI_MC6_RESIDENCY               0x000003FD
> 
> @@ -814,6 +835,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
>    AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as
> MSR_CORE_C6_RESIDENCY in SDM.
>  **/
>  #define MSR_XEON_PHI_CORE_C6_RESIDENCY           0x000003FF
> 
> @@ -832,6 +854,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC3_CTL is defined as MSR_MC3_CTL in SDM.
>  **/
>  #define MSR_XEON_PHI_MC3_CTL                     0x0000040C
> 
> @@ -850,6 +873,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC3_STATUS is defined as MSR_MC3_STATUS in
> SDM.
>  **/
>  #define MSR_XEON_PHI_MC3_STATUS                  0x0000040D
> 
> @@ -868,6 +892,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
>  **/
>  #define MSR_XEON_PHI_MC3_ADDR                    0x0000040E
> 
> @@ -886,6 +911,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC4_CTL is defined as MSR_MC4_CTL in SDM.
>  **/
>  #define MSR_XEON_PHI_MC4_CTL                     0x00000410
> 
> @@ -904,6 +930,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC4_STATUS is defined as MSR_MC4_STATUS in
> SDM.
>  **/
>  #define MSR_XEON_PHI_MC4_STATUS                  0x00000411
> 
> @@ -925,6 +952,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
>  **/
>  #define MSR_XEON_PHI_MC4_ADDR                    0x00000412
> 
> @@ -943,6 +971,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC5_CTL is defined as MSR_MC5_CTL in SDM.
>  **/
>  #define MSR_XEON_PHI_MC5_CTL                     0x00000414
> 
> @@ -961,6 +990,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC5_STATUS is defined as MSR_MC5_STATUS in
> SDM.
>  **/
>  #define MSR_XEON_PHI_MC5_STATUS                  0x00000415
> 
> @@ -979,6 +1009,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR);
>    AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
>  **/
>  #define MSR_XEON_PHI_MC5_ADDR                    0x00000416
> 
> @@ -996,6 +1027,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
>    @endcode
> +  @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as
> IA32_VMX_EPT_VPID_ENUM in SDM.
>  **/
>  #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM      0x0000048C
> 
> @@ -1014,6 +1046,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
>    @endcode
> +  @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as
> IA32_VMX_FMFUNC in SDM.
>  **/
>  #define MSR_XEON_PHI_IA32_VMX_FMFUNC             0x00000491
> 
> @@ -1033,6 +1066,7 @@ typedef union {
> 
>    Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
>    @endcode
> +  @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as
> MSR_RAPL_POWER_UNIT in SDM.
>  **/
>  #define MSR_XEON_PHI_RAPL_POWER_UNIT             0x00000606
> 
> @@ -1092,6 +1126,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
>    AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as
> MSR_PKG_C2_RESIDENCY in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_C2_RESIDENCY            0x0000060D
> 
> @@ -1111,6 +1146,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
>    AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as
> MSR_PKG_POWER_LIMIT in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_POWER_LIMIT             0x00000610
> 
> @@ -1128,6 +1164,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
>    @endcode
> +  @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as
> MSR_PKG_ENERGY_STATUS in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_ENERGY_STATUS           0x00000611
> 
> @@ -1145,6 +1182,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
>    @endcode
> +  @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as
> MSR_PKG_PERF_STATUS in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_PERF_STATUS             0x00000613
> 
> @@ -1164,6 +1202,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
>    AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_PKG_POWER_INFO is defined as
> MSR_PKG_POWER_INFO in SDM.
>  **/
>  #define MSR_XEON_PHI_PKG_POWER_INFO              0x00000614
> 
> @@ -1183,6 +1222,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
>    AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as
> MSR_DRAM_POWER_LIMIT in SDM.
>  **/
>  #define MSR_XEON_PHI_DRAM_POWER_LIMIT            0x00000618
> 
> @@ -1200,6 +1240,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
>    @endcode
> +  @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as
> MSR_DRAM_ENERGY_STATUS in SDM.
>  **/
>  #define MSR_XEON_PHI_DRAM_ENERGY_STATUS          0x00000619
> 
> @@ -1218,6 +1259,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
>    @endcode
> +  @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as
> MSR_DRAM_PERF_STATUS in SDM.
>  **/
>  #define MSR_XEON_PHI_DRAM_PERF_STATUS            0x0000061B
> 
> @@ -1236,6 +1278,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
>    AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as
> MSR_DRAM_POWER_INFO in SDM.
>  **/
>  #define MSR_XEON_PHI_DRAM_POWER_INFO             0x0000061C
> 
> @@ -1255,6 +1298,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
>    AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as
> MSR_PP0_POWER_LIMIT in SDM.
>  **/
>  #define MSR_XEON_PHI_PP0_POWER_LIMIT             0x00000638
> 
> @@ -1273,6 +1317,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
>    @endcode
> +  @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as
> MSR_PP0_ENERGY_STATUS in SDM.
>  **/
>  #define MSR_XEON_PHI_PP0_ENERGY_STATUS           0x00000639
> 
> @@ -1290,6 +1335,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
>    @endcode
> +  @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as
> MSR_CONFIG_TDP_NOMINAL in SDM.
>  **/
>  #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL          0x00000648
> 
> @@ -1307,6 +1353,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
>    @endcode
> +  @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as
> MSR_CONFIG_TDP_LEVEL1 in SDM.
>  **/
>  #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1           0x00000649
> 
> @@ -1324,6 +1371,7 @@ typedef union {
> 
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
>    @endcode
> +  @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as
> MSR_CONFIG_TDP_LEVEL2 in SDM.
>  **/
>  #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2           0x0000064A
> 
> @@ -1342,6 +1390,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
>    AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as
> MSR_CONFIG_TDP_CONTROL in SDM.
>  **/
>  #define MSR_XEON_PHI_CONFIG_TDP_CONTROL          0x0000064B
> 
> @@ -1360,6 +1409,7 @@ typedef union {
>    Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
>    AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
>    @endcode
> +  @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as
> MSR_TURBO_ACTIVATION_RATIO in SDM.
>  **/
>  #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO      0x0000064C
> 
> @@ -1381,6 +1431,7 @@ typedef union {
>    Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
>    AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
>    @endcode
> +  @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as
> MSR_CORE_PERF_LIMIT_REASONS in SDM.
>  **/
>  #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS     0x00000690
> 
> --
> 2.9.3.windows.2



^ permalink raw reply	[flat|nested] 22+ messages in thread

end of thread, other threads:[~2016-09-06 17:27 UTC | newest]

Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-09-06 11:38 [Patch 00/20] add MSR reference from SDM in comment Jeff Fan
2016-09-06 11:38 ` [Patch 01/20] UefiCpuPkg/ArchitecturalMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 02/20] UefiCpuPkg/AtomMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 03/20] UefiCpuPkg/BroadwellMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 04/20] UefiCpuPkg/Core2Msr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 05/20] UefiCpuPkg/CoreMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 06/20] UefiCpuPkg/HaswellEMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 07/20] UefiCpuPkg/HaswellMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 08/20] UefiCpuPkg/IvyBridgeMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 09/20] UefiCpuPkg/NehalemMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 10/20] UefiCpuPkg/P6Msr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 11/20] UefiCpuPkg/Pentium4Msr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 12/20] UefiCpuPkg/PentiumMMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 13/20] UefiCpuPkg/PentiumMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 14/20] UefiCpuPkg/SandyBridgeMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 15/20] UefiCpuPkg/SilvermontMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 16/20] UefiCpuPkg/SkylakeMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 17/20] UefiCpuPkg/Xeon5600Msr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 18/20] UefiCpuPkg/XeonDMsr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 19/20] UefiCpuPkg/XeonE7Msr.h: " Jeff Fan
2016-09-06 11:38 ` [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: " Jeff Fan
2016-09-06 17:27   ` Mudusuru, Giri P

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