From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E14021A1EC7 for ; Wed, 21 Sep 2016 13:33:23 -0700 (PDT) Received: from E107800.Emea.Arm.com (e107800.emea.arm.com [10.1.33.85]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id u8LKXKhb008453; Wed, 21 Sep 2016 21:33:21 +0100 From: evan.lloyd@arm.com To: edk2-devel@ml01.01.org Cc: Ard Biesheuvel , Leif Lindholm , Ryan Harkin Date: Wed, 21 Sep 2016 21:33:13 +0100 Message-Id: <20160921203315.11204-2-evan.lloyd@arm.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160921203315.11204-1-evan.lloyd@arm.com> References: <20160921203315.11204-1-evan.lloyd@arm.com> Subject: [PATCH 1/3] ArmPlatformPkg: Fix PL011 FIFO size test X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Sep 2016 20:33:24 -0000 From: Evan Lloyd This change updates PL011UartInitializePort to compare ReceiveFifoDepth with the correct hardware FIFO size instead of the constant 32 used previously. This corrects a minor bug where a request for a fifo size > 15 and < 32 would not have been honoured on a system with a 16 byte FIFO. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar Signed-off-by: Evan Lloyd --- ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c index 3748972acbfc80f1077b9b928756a72cc77b5c75..b3ea138bf60b93a1000dd29aedaad206f2d15f2b 100644 --- a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c +++ b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c @@ -79,17 +79,18 @@ PL011UartInitializePort ( UINT32 Divisor; UINT32 Integer; UINT32 Fractional; + UINT32 HardwareFifoDepth; + HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \ + > PL011_VER_R1P4) \ + ? 32 : 16 ; // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept // 1 char buffer as the minimum FIFO size. Because everything can be rounded // down, there is no maximum FIFO size. - if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= 32)) { + if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) { // Enable FIFO LineControl = PL011_UARTLCR_H_FEN; - if (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) > PL011_VER_R1P4) - *ReceiveFifoDepth = 32; - else - *ReceiveFifoDepth = 16; + *ReceiveFifoDepth = HardwareFifoDepth; } else { // Disable FIFO LineControl = 0; -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")