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Ip=[217.140.96.140]; Helo=[nebula.arm.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR08MB0805 X-MC-Unique: FY366_lPMjaf6pdpt9a_GA-1 Subject: Re: [RESEND PATCH] ArmVirtPkg: Bit width adaption in ASSERT() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 24 Oct 2016 03:01:53 -0000 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Hello Laszlo, On Fri, Oct 21, 2016 at 10:02:45AM +0200, Laszlo Ersek wrote: > On 10/21/16 07:50, Dennis Chen wrote: > > Since All the GIC base address variables has been aligned to 64-bit, it= =20 > > doesn't make sense to continue use MAX_UINT32 in ASSERT() statement, so= =20 > > this patch uses MAX_UINTN to adapt to this kind of change. > >=20 > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Cc: Ard Biesheuvel > > Cc: Leif Lindholm > > Cc: Laszlo Ersek > > Signed-off-by: Dennis Chen > > --- > > ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > >=20 > > diff --git a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c b= /ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c > > index 64afc4d..6488061 100644 > > --- a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c > > +++ b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c > > @@ -79,11 +79,11 @@ ArmVirtGicArchLibConstructor ( > > =20 > > // RegProp[0..1] =3D=3D { GICD base, GICD size } > > DistBase =3D SwapBytes64 (Reg[0]); > > - ASSERT (DistBase < MAX_UINT32); > > + ASSERT (DistBase < MAX_UINTN); > > =20 > > // RegProp[2..3] =3D=3D { GICR base, GICR size } > > RedistBase =3D SwapBytes64 (Reg[2]); > > - ASSERT (RedistBase < MAX_UINT32); > > + ASSERT (RedistBase < MAX_UINTN); > > =20 > > PcdSet64 (PcdGicDistributorBase, DistBase); > > PcdSet64 (PcdGicRedistributorsBase, RedistBase); > > @@ -117,8 +117,8 @@ ArmVirtGicArchLibConstructor ( > > =20 > > DistBase =3D SwapBytes64 (Reg[0]); > > CpuBase =3D SwapBytes64 (Reg[2]); > > - ASSERT (DistBase < MAX_UINT32); > > - ASSERT (CpuBase < MAX_UINT32); > > + ASSERT (DistBase < MAX_UINTN); > > + ASSERT (CpuBase < MAX_UINTN); > > =20 > > PcdSet64 (PcdGicDistributorBase, DistBase); > > PcdSet64 (PcdGicInterruptInterfaceBase, CpuBase); > >=20 >=20 > Ard, can you please handle this iteration of the patch as well? >=20 > I do have one suggestion, for the subject: >=20 > ArmVirtPkg/ArmVirtGicArchLib: adapt ASSERT()s to 64-bit base addresses >=20 > If you guys agree, I think it can be done on commit. With that, > I think Ard will not have any reason to reject this nice suggestion :), so = do I. so it's a deal... Thanks, Dennis >=20 > Acked-by: Laszlo Ersek >=20 > Thanks > Laszlo >=20