From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4D84781DC1 for ; Fri, 28 Oct 2016 08:21:09 -0700 (PDT) Received: by mail-wm0-x233.google.com with SMTP id e69so108798255wmg.0 for ; Fri, 28 Oct 2016 08:21:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=2RLlfhhBBs1c16yzXTN+gf10kX2jHuFWky2hnvqdEsU=; b=Q4bwkYhxmyAX1CnNigBy9x7Qy/ntvmWZ+epzTyDJLgR/2dm9bqSYQuzCPC92+NCSHv SNHkX5L/yKhtBOt2l+Nq7LuY/fpnatKKnfI8eniwbwdH+MMDUYy6hqee14l8HRBPxLKk jcgiZfI/Atmen3uVoSGReSCKgB6rth3/+1PMY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=2RLlfhhBBs1c16yzXTN+gf10kX2jHuFWky2hnvqdEsU=; b=NR/5nVnfzsKtBYTBQFHjGYeSaPbt3jVeMICUWwknX9H6wc166/3W4xu20VaSGOPQh1 5Qdun/BTbDLftN3fmo0PKuZaR6023qdEuZnFZT283Bpii35LTn8EdjfLLG8KL0W5GZQH fD1sB3GRelQLXVUmdwn6q0DokGJQcgB8dSK8a44p2yGFxKS1sIMnFnd1i+Ignd2iM3iy HHp9lapSEX7jZNom9nTHOBAitjZnX4128WK919amSI8ZRPeGjewPn067klTRmgA4lwKl lHk/gUsB88SK9nJtLRRr/J+agdVE3jrzmm36taeAFRLZL5Kl4lBjSoFp8lFEHFezllRp kFKg== X-Gm-Message-State: ABUngvew29p5/f5Z33jH5HgTcutsM1n5Hnqm3PGKwY8c4dVtjxdb5yhPdK/tGHVukvI90F3J X-Received: by 10.28.215.6 with SMTP id o6mr3152277wmg.124.1477668068417; Fri, 28 Oct 2016 08:21:08 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id hb5sm14635619wjc.5.2016.10.28.08.21.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 28 Oct 2016 08:21:07 -0700 (PDT) Date: Fri, 28 Oct 2016 16:21:06 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20161028152106.GA1161@bivouac.eciton.net> References: <1477654974-5598-1-git-send-email-ard.biesheuvel@linaro.org> <1477654974-5598-2-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1477654974-5598-2-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH 1/3] ArmPkg RVCT: add ADRL/LDRL macro equivalents X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Oct 2016 15:21:09 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Oct 28, 2016 at 12:42:52PM +0100, Ard Biesheuvel wrote: > The GCC ARM builds have access to ADRL/LDRL macros that emit relative > symbol references, i.e., references that do not require fixing up at > load time (or FV generation time for XIP modules) > > Implement equivalent functionality for RVCT: note that this does not > use movw/movt pairs, but the more compatible add/add/add or add/add/ldr > sequences (which Clang does not support, unfortunately, hence the use > of movw/movt for the GCC toolchain family) > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel Not tested, but looks sensible. Reviewed-by: Leif Lindholm > --- > ArmPkg/Include/AsmMacroIoLib.inc | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/ArmPkg/Include/AsmMacroIoLib.inc b/ArmPkg/Include/AsmMacroIoLib.inc > index c9cad5230c94..4bc3146fb399 100644 > --- a/ArmPkg/Include/AsmMacroIoLib.inc > +++ b/ArmPkg/Include/AsmMacroIoLib.inc > @@ -26,4 +26,24 @@ > ldr $Reg, =($Data) > MEND > > + MACRO > + adrll $Reg, $Symbol > + add $Reg, pc, #-8 > + RELOC R_ARM_ALU_PC_G0_NC, $Symbol > + add $Reg, $Reg, #-4 > + RELOC R_ARM_ALU_PC_G1_NC, $Symbol > + add $Reg, $Reg, #0 > + RELOC R_ARM_ALU_PC_G2, $Symbol > + MEND > + > + MACRO > + ldrl $Reg, $Symbol > + add $Reg, pc, #-8 > + RELOC R_ARM_ALU_PC_G0_NC, $Symbol > + add $Reg, $Reg, #-4 > + RELOC R_ARM_ALU_PC_G1_NC, $Symbol > + ldr $Reg, [$Reg, #0] > + RELOC R_ARM_LDR_PC_G2, $Symbol > + MEND > + > END > -- > 2.7.4 >