From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22c.google.com (mail-wm0-x22c.google.com [IPv6:2a00:1450:400c:c09::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 375E381CE2 for ; Tue, 1 Nov 2016 15:32:30 -0700 (PDT) Received: by mail-wm0-x22c.google.com with SMTP id p190so232881142wmp.1 for ; Tue, 01 Nov 2016 15:32:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=tlQbq8LrQMVOVrv7O9FKSWeS01thTrPsNcTq26WGgGA=; b=CpPOYz1ZfU19i+fDe09CdXSnZboYZ9/pr6hczYv5dg3qXlGy17ueHEWMX/Yo/HRYRU TJGX8UPhdmqzjw3a7s+0F7XftZZIs59k/3v7BtM81/VekTOKCiQkzHkTRPuNsK7vlR8M akm9NrUtmkhpihtDiDxmVkge67uuytsSnERV8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=tlQbq8LrQMVOVrv7O9FKSWeS01thTrPsNcTq26WGgGA=; b=bRdQcfFASDBRWKAmRjDfGW0ese/ZtJttWudEfYHpBV3oP5yQ2RavRO3ZT+SbWH1vSQ jXsNlmjHsQ0i0OY8zofhXVaVbRrojGkRiO9DF8A8buHBsim8y9Nn7thsdJrbnD0tVA97 8Ik0RXqTN9iALlCmt5iOpXqtRaSdgTi1gyA/+1rp3ixCEC7DqQAUFL3zlN/ddHKYpUHy bSAfQMXEa9cHZnHTuI+872BADLEQbRlFlaqtp+uvqNAX15laDF6o2w+aH/QgRdcbtY48 GEhcvACvnDCstjwt9q+Zk/7xbfdjGK+l3jd36TpU4HelLSxp0nzy17OLTZNUUyjEwPwq 413g== X-Gm-Message-State: ABUngvfRtxBljVInJRmq/mRwYsg3/G2yc0Y30xANMOeYJuz9av556A3WzFpwxZ9In1LUsRFf X-Received: by 10.28.169.74 with SMTP id s71mr208788wme.1.1478039550231; Tue, 01 Nov 2016 15:32:30 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 132sm32813276wmn.16.2016.11.01.15.32.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Nov 2016 15:32:29 -0700 (PDT) Date: Tue, 1 Nov 2016 22:32:27 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20161101223227.GP1161@bivouac.eciton.net> References: <1477937590-10361-1-git-send-email-ard.biesheuvel@linaro.org> <1477937590-10361-5-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1477937590-10361-5-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH 4/5] ArmPkg/CpuDxe: set DmaBufferAlignment according to CWG X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Nov 2016 22:32:30 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Oct 31, 2016 at 06:13:09PM +0000, Ard Biesheuvel wrote: > The DmaBufferAlignment currently defaults to 4, which is dangerously > small and may result in lost data on platform that perform non-coherent > DMA. So instead, take the CWG value from the cache info registers. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Drivers/CpuDxe/CpuDxe.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c > index d089cb2d119f..ddc64fd255a0 100644 > --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c > +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c > @@ -225,7 +225,7 @@ EFI_CPU_ARCH_PROTOCOL mCpu = { > CpuGetTimerValue, > CpuSetMemoryAttributes, > 0, // NumberOfTimers > - 4, // DmaBufferAlignment > + 2048, // DmaBufferAlignment > }; > > EFI_STATUS > @@ -239,6 +239,8 @@ CpuDxeInitialize ( > > InitializeExceptions (&mCpu); > > + mCpu.DmaBufferAlignment = ArmCacheWritebackGranule (); > + Could we hide the internal structure of mCpu here by moving this to a helper function and calling InitializeDma (&mCpu); (or something)? > Status = gBS->InstallMultipleProtocolInterfaces ( > &mCpuHandle, > &gEfiCpuArchProtocolGuid, &mCpu, > -- > 2.7.4 >