From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CFD0281DFC for ; Mon, 14 Nov 2016 09:27:20 -0800 (PST) Received: by mail-wm0-x231.google.com with SMTP id t79so111322961wmt.0 for ; Mon, 14 Nov 2016 09:27:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=RFhutZB3Vee6A6ccwTRDRJLcaRHNctUWpHTJ56XpRME=; b=TRyqzRFSWFtP8ff4SxUhLxTfRch1FVCd0IYXrjUVtuhWXNN2wejnC4ylPC/W3n+61G C1fq7FxQ+V0KRvayVF7MexlyebWtcxSj5hYXT3SCsR7h8gPB5cdvEdSdp98jk+UmzHyg W8V9fqmoefobFQU3Wog/uz/wIUpdfvnlz62hw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=RFhutZB3Vee6A6ccwTRDRJLcaRHNctUWpHTJ56XpRME=; b=WGvipHgVW18Ccmh+k9VRLLLwlx3LmEuiyHdMYUqz4aDHREsd5+GyDUo0cZoyemOIDL IR343954nLDbnIYWJGO9xeWDy19+iwWkb89HXHOOSLGESVAldnbLOjLXApt8WFM0oBX6 kTpUe0HSBLlJhFIXr70ebnUBt9nF5gxAw25KyOJol4oVAs9KWGxXwUQAkgUarTAi4hc+ DLFfzEw8i/gDsi+Dy3v/5trisIWifKrumRS+K4hw9tP+7KY5N6ZaxpOD3ZYxCX3Nnm8m ZJy1EDjQW0YfZ0EP0w1ew03iyr57vo87Lf44bRAkG6w/BUqadKoqW9q4+DdySyt3diwu c77g== X-Gm-Message-State: ABUngvcP0ZXi8hqAJtgwqgDLcObTtkSnfUUxCh6oBsMNGJoK0/KIwoYN+v2P1lH/fxdwUxdO X-Received: by 10.194.115.70 with SMTP id jm6mr7303321wjb.140.1479144444094; Mon, 14 Nov 2016 09:27:24 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 63sm16419001wmg.2.2016.11.14.09.27.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Nov 2016 09:27:23 -0800 (PST) Date: Mon, 14 Nov 2016 17:27:21 +0000 From: Leif Lindholm To: Haojian Zhuang Cc: ryan.harkin@linaro.org, edk2-devel@lists.01.org, ard.biesheuvel@linaro.org Message-ID: <20161114172721.GB27644@bivouac.eciton.net> References: <1479019678-12621-1-git-send-email-haojian.zhuang@linaro.org> <1479019678-12621-10-git-send-email-haojian.zhuang@linaro.org> MIME-Version: 1.0 In-Reply-To: <1479019678-12621-10-git-send-email-haojian.zhuang@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v5 9/9] PL180: update for indentifying SD X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Nov 2016 17:27:21 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sun, Nov 13, 2016 at 02:47:58PM +0800, Haojian Zhuang wrote: > When CMD6 & ACMD51 are added into indentifying SD process, PL180 > should also support CMD6 & ACMD51. Otherwise, it'll hang when > system tries to read expected data. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Haojian Zhuang > Tested-by: Ryan Harkin The change as such is fine. (More than fine.) However, should this not be added before the current 6/9, in order to not leave a gap of commits that fail to boot? Could I even push it independently of the series? Regards, Leif > --- > ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c | 29 ++++++++++++++++++++------- > 1 file changed, 22 insertions(+), 7 deletions(-) > > diff --git a/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c b/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c > index 5526aac..b2ba4c0 100644 > --- a/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c > +++ b/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c > @@ -63,11 +63,6 @@ MciIsReadOnly ( > return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_WPROT); > } > > -#if 0 > -//Note: This function has been commented out because it is not used yet. > -// This function could be used to remove the hardcoded BlockLen used > -// in MciPrepareDataPath > - > // Convert block size to 2^n > STATIC > UINT32 > @@ -87,7 +82,6 @@ GetPow2BlockLen ( > > return Pow2BlockLen; > } > -#endif > > VOID > MciPrepareDataPath ( > @@ -126,6 +120,23 @@ MciSendCommand ( > MciPrepareDataPath (MCI_DATACTL_CARD_TO_CONT); > } else if ((MmcCmd == MMC_CMD24) || (MmcCmd == MMC_CMD20)) { > MciPrepareDataPath (MCI_DATACTL_CONT_TO_CARD); > + } else if (MmcCmd == MMC_CMD6) { > + MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF); > + MmioWrite32 (MCI_DATA_LENGTH_REG, 64); > +#ifndef USE_STREAM > + MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | GetPow2BlockLen (64)); > +#else > + MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | MCI_DATACTL_STREAM_TRANS); > +#endif > + } else if (MmcCmd == MMC_ACMD51) { > + MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF); > + /* SCR register is 8 bytes long. */ > + MmioWrite32 (MCI_DATA_LENGTH_REG, 8); > +#ifndef USE_STREAM > + MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | GetPow2BlockLen (8)); > +#else > + MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | MCI_DATACTL_STREAM_TRANS); > +#endif > } > > // Create Command for PL180 > @@ -223,7 +234,11 @@ MciReadBlockData ( > > // Read data from the RX FIFO > Loop = 0; > - Finish = MMCI0_BLOCKLEN / 4; > + if (Length < MMCI0_BLOCKLEN) { > + Finish = Length / 4; > + } else { > + Finish = MMCI0_BLOCKLEN / 4; > + } > > // Raise the TPL at the highest level to disable Interrupts. > Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL); > -- > 2.7.4 >