From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F01D281E60 for ; Mon, 14 Nov 2016 18:43:10 -0800 (PST) Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 50A1531B333; Tue, 15 Nov 2016 02:43:15 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-50.phx2.redhat.com [10.3.116.50]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uAF2hCZv032444; Mon, 14 Nov 2016 21:43:14 -0500 From: Laszlo Ersek To: edk2-devel-01 Cc: Jordan Justen , Paolo Bonzini Date: Tue, 15 Nov 2016 03:43:06 +0100 Message-Id: <20161115024308.30612-2-lersek@redhat.com> In-Reply-To: <20161115024308.30612-1-lersek@redhat.com> References: <20161115024308.30612-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Tue, 15 Nov 2016 02:43:15 +0000 (UTC) Subject: [PATCH 1/3] OvmfPkg/SmmControl2Dxe: select broadcast SMI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Nov 2016 02:43:11 -0000 When writing to IO port 0xB2 (ICH9_APM_CNT), QEMU by default injects an SMI only on the VCPU that is writing the port. This has exposed corner cases and strange behavior with edk2 code, which generally expects a software SMI to affect all CPUs at once. The QEMU patch hw/isa/lpc_ich9: inject SMI on all VCPUs if APM_STS == 'Q' adds a side-channel / backdoor to QEMU that enables the firmware to request a broadcast SMI; namely, by setting IO port 0xB3 (ICH9_APM_STS) to value 0x51 ('Q') first. (The default behavior cannot be changed because SeaBIOS depends on it.) Utilize this feature in OVMF's EFI_SMM_CONTROL2_PROTOCOL.Trigger() method. The change has no effect on QEMUs that lack the above patch. Cc: Jordan Justen Cc: Paolo Bonzini Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=230 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 6 ++++-- OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c | 18 +++++++++++++++++- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h index 4dc2c39901c1..acc05f84b18c 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -91,8 +91,10 @@ // // IO ports // -#define ICH9_APM_CNT 0xB2 -#define ICH9_APM_STS 0xB3 +#define ICH9_APM_CNT 0xB2 + +#define ICH9_APM_STS 0xB3 +#define QEMU_ICH9_APM_STS_BROADCAST_SMI 'Q' // // IO ports relative to PMBASE diff --git a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c index 82549b0a7e35..2c987c0cc558 100644 --- a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c +++ b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c @@ -107,10 +107,26 @@ SmmControl2DxeTrigger ( // report about hardware status, while this register is fully governed by // software. // + // On the QEMU platform, we use the status register to request a "broadcast" + // SMI; i.e., to bring all VCPUs into SMM at once. Edk2 handles the case when + // the SMI is raised only on the processor that calls Trigger(), but + // + // - if the processor executing Trigger() is an AP, then the resultant AP-BSP + // synchronization is time consuming and computation-hungry, + // + // - edk2 modules that deal with SMIs generally expect / prefer a software + // SMI to affect all CPUs at once; unicast SMIs have exposed obscure corner + // cases. + // + // Note that we exploit the fact that the SMM_CORE never passes a non-NULL + // DataPort pointer (that is, we exploit that it doesn't care about the + // status register value). + // // Write to the status register first, as this won't trigger the SMI just // yet. Then write to the control register. // - IoWrite8 (ICH9_APM_STS, DataPort == NULL ? 0 : *DataPort); + ASSERT (DataPort == NULL); + IoWrite8 (ICH9_APM_STS, QEMU_ICH9_APM_STS_BROADCAST_SMI); IoWrite8 (ICH9_APM_CNT, CommandPort == NULL ? 0 : *CommandPort); return EFI_SUCCESS; } -- 2.9.2