From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from SMTP.CITRIX.COM (smtp.citrix.com [66.165.176.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6C9A081F5B for ; Thu, 8 Dec 2016 07:53:27 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.33,320,1477958400"; d="scan'208";a="393762211" From: Anthony PERARD To: , CC: Anthony PERARD Date: Thu, 8 Dec 2016 15:33:36 +0000 Message-ID: <20161208153340.2285-11-anthony.perard@citrix.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161208153340.2285-1-anthony.perard@citrix.com> References: <20161208153340.2285-1-anthony.perard@citrix.com> MIME-Version: 1.0 Subject: [PATCH RFC 10/14] UefiCpuPkg/BaseXApicX2ApicLib: Fix initialisation on my system and ... X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Dec 2016 15:53:28 -0000 Content-Type: text/plain declare more exported function, ReadLocalApicReg and WriteLocalApicReg. On my system (running OVMF inside a Xen PVH guest), writing the interrupt information (to XAPIC_LVT_TIMER_OFFSET) would also reset the init-count register, thus disabling the timer. --- UefiCpuPkg/Include/Library/LocalApicLib.h | 40 ++++++++++++++++++++++ .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 10 +++--- 2 files changed, 45 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h index fc980bc..ab621f2 100644 --- a/UefiCpuPkg/Include/Library/LocalApicLib.h +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h @@ -48,6 +48,46 @@ SetLocalApicBaseAddress ( ); /** + Read from a local APIC register. + + This function reads from a local APIC register either in xAPIC or x2APIC mode. + It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be + accessed using multiple 32-bit loads or stores, so this function only performs + 32-bit read. + + @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode. + It must be 16-byte aligned. + + @return 32-bit Value read from the register. +**/ +UINT32 +EFIAPI +ReadLocalApicReg ( + IN UINTN MmioOffset + ); + +/** + Write to a local APIC register. + + This function writes to a local APIC register either in xAPIC or x2APIC mode. + It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be + accessed using multiple 32-bit loads or stores, so this function only performs + 32-bit write. + + if the register index is invalid or unsupported in current APIC mode, then ASSERT. + + @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode. + It must be 16-byte aligned. + @param Value Value to be written to the register. +**/ +VOID +EFIAPI +WriteLocalApicReg ( + IN UINTN MmioOffset, + IN UINT32 Value + ); + +/** Get the current local APIC mode. If local APIC is disabled, then ASSERT. diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index e690d2a..f84a40a 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -820,11 +820,6 @@ InitializeApicTimer ( // InitializeLocalApicSoftwareEnable (TRUE); - // - // Program init-count register. - // - WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount); - if (DivideValue != 0) { ASSERT (DivideValue <= 128); ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue)); @@ -848,6 +843,11 @@ InitializeApicTimer ( LvtTimer.Bits.Mask = 0; LvtTimer.Bits.Vector = Vector; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); + + // + // Program init-count register. + // + WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount); } /** -- Anthony PERARD