From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 725788190C for ; Mon, 26 Dec 2016 03:21:10 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP; 26 Dec 2016 03:21:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,404,1477983600"; d="scan'208";a="916215823" Received: from jfan12-desk.ccr.corp.intel.com ([10.239.9.5]) by orsmga003.jf.intel.com with ESMTP; 26 Dec 2016 03:21:09 -0800 From: Jeff Fan To: edk2-devel@lists.01.org Cc: Feng Tian , Kinney, Michael D , Ruiyu Ni Date: Mon, 26 Dec 2016 19:20:59 +0800 Message-Id: <20161226112102.25512-4-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20161226112102.25512-1-jeff.fan@intel.com> References: <20161226112102.25512-1-jeff.fan@intel.com> Subject: [PATCH 3/6] UefiCpuPkg/MpInitLib: Move save/restore interrupt to SwitchBSPWorker() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Dec 2016 11:21:10 -0000 During switching BSP phase, we need to disable CPU interruput to prevent stack crashed by Timer interrupt handle. But when we enabled source debugging feature, debug timer interrupt handler (existing on both PEI and DXE) also could crash the stack used during switching BSP. So,we need to move save/restore interrupt to SwitchBSPWorker(). Cc: Feng Tian Cc: Kinney, Michael D Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 19 ------------------- UefiCpuPkg/Library/MpInitLib/MpLib.c | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c index 1204abd..733a9fb 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -646,29 +646,10 @@ MpInitLibSwitchBSP ( ) { EFI_STATUS Status; - BOOLEAN OldInterruptState; - // - // Before send both BSP and AP to a procedure to exchange their roles, - // interrupt must be disabled. This is because during the exchange role - // process, 2 CPU may use 1 stack. If interrupt happens, the stack will - // be corrupted, since interrupt return address will be pushed to stack - // by hardware. - // - OldInterruptState = SaveAndDisableInterrupts (); - - // - // Mask LINT0 & LINT1 for the old BSP - // - DisableLvtInterrupts (); Status = SwitchBSPWorker (ProcessorNumber, EnableOldBSP); - // - // Restore interrupt state. - // - SetInterruptState (OldInterruptState); - return Status; } diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index e5842ef..9dae827 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -1511,6 +1511,21 @@ SwitchBSPWorker ( UINTN CallerNumber; CPU_STATE State; MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; + BOOLEAN OldInterruptState; + + // + // Before send both BSP and AP to a procedure to exchange their roles, + // interrupt must be disabled. This is because during the exchange role + // process, 2 CPU may use 1 stack. If interrupt happens, the stack will + // be corrupted, since interrupt return address will be pushed to stack + // by hardware. + // + OldInterruptState = SaveAndDisableInterrupts (); + + // + // Mask LINT0 & LINT1 for the old BSP + // + DisableLvtInterrupts (); CpuMpData = GetCpuMpData (); @@ -1593,6 +1608,12 @@ SwitchBSPWorker ( // CpuMpData->BspNumber = (UINT32) ProcessorNumber; + // + // Restore interrupt state. + // + SetInterruptState (OldInterruptState); + + return EFI_SUCCESS; } -- 2.9.3.windows.2